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Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures

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Published:24 November 2008Publication History

ABSTRACT

Device model evaluation is one of the most time-consuming tasks in analog simulators such as SPICE. Graphics Processing Unit (GPU) architectures allow massive utilization of vector data on SIMD architectures. In this paper, the formulation of double precision device model equations into a form compatible with stream computing is presented. We show data on isolating typical bottlenecks, especially the communication and kernel call overheads. Our results indicate speedup of up to 20X when counting overheads, and up to 50X when using techniques to overcome these overheads. In particular, we show that our techniques are valid for small device counts, which is typically a well known problem for accelerated parallel computing with communications overheads.

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  1. Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures

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            cover image ACM Other conferences
            IFMT '08: Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
            November 2008
            121 pages
            ISBN:9781605584072
            DOI:10.1145/1463768

            Copyright © 2008 ACM

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            Association for Computing Machinery

            New York, NY, United States

            Publication History

            • Published: 24 November 2008

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