Sang-Hun Yoon
ABSTRACT
In this paper, an area efficient digital filter design method is proposed. The conventional area efficient filter design methods have the problems of long critical path delay since they make deep logic depth due to adder sharing. In this paper, we propose a method which can reduce filter size using the redundancy of the signed digit (SD) number system based on the flattened-coefficient method which can share adders while maintain the critical path delay. Simulation results show that the proposed structure can save the number of adders and registers 22% and 26%, respectively, than the conventional methods can do.
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Index Terms
- An area reduction method for digital filter using redundancy of SD number system
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