Abdul-Rahman Elshafei
ABSTRACT
This work proposes a scalable architecture for implementing a mixed-norm LMS-LMF adaptive algorithm using a 16-bit fixed-point arithmetic representation. The hardware scalability allows flexibility in the choice of selecting the order of the filter without redesigning the hardware. The filter also allows flexibility in using application specific sampling frequencies.
The hardware architecture was implemented using a Virtex-4 FPGA ML402 board. A 2nd order prototype was tested through both hardware and software simulations. According to the synthesis and the simulation results obtained, the adaptive filter coefficients would converge in less than 17μs with accuracy greater than 95%.
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Index Terms
- Scalable FPGA implementation for mixed-norm LMS-LMF adaptive filters
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