Noriko Takagi
ABSTRACT
In a single-chip multiprocessor (CMP), the last-level cache and its lower memory hierarchy components are typically shared by multiple processors. Conflicts in these resources lead to poor overall performance of the CMP and/or unpredictable performance of the individual cores. If applications on different cores have different performance constraints, even though these constraints can be satisfied by dynamic voltage and frequency scaling (DVFS) control of each core, conflicts in shared resources will lead to increased power consumption. Therefore, in the present paper, we derive a condition whereby, under resource conflicts, the total power consumption is minimized by a newly developed power consumption model and propose a method by which to minimize the power consumption of CMPs by cooperative access control of multiple shared resources and DVFS control. Experimental results reveal that the proposed technique can reduce power consumption by 15% on average in a dual-core CMP and by 13% in a quad-core CMP, as compared to the case in which only DVFS control is applied.
- T. Austin, et al., Simplescalar: An infrastructure for computer system modeling. Computer, 35(2):59--67, February 2002. Google Scholar
Digital Library
- D. Brooks, et al., Wattch: A framework for architectural-level power analysis and optimizations. In In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83--94, June 2000. Google ScholarDigital Library
- C. Cascaval, et al., Compile-time based performance prediction. In In Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing, pages 365--379, 1999. Google ScholarDigital Library
- J. Chang and G.S. Sohi. Cooperative cache partitioning for chip multiprocessors. In Proceedings of the 21st annual international conference on Supercomputing, pages 242--252, June 2007. Google ScholarDigital Library
- H.264/AVC Software Coordination. H.264/AVC reference software. http://iphome.hhi.de/suehring/tml.Google Scholar
- S. Kim, et al., Fair cache sharing and partitioning in a chip multiprocessor architecture. In Proceedings of the 13th International Conference on Parallel Architecture and Compilation Techniques, pages 111--122, September 2004. Google ScholarDigital Library
- K.J. Nesbit, et al., Fair queuing memory systems. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 208--222, 2006. Google ScholarDigital Library
- M.K. Qureshi and Y.N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 423--432, December 2006. Google ScholarDigital Library
- Standard Performance Evaluation Corporation (SPEC). SPEC CPU2000. http://www.specbench.org.Google Scholar
- G.E. Suh, et al., A new memory monitoring scheme for memory-aware scheduling and partitioning. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture, pages 117--128, February 2002. Google ScholarDigital Library
- R. Watanabe, et al., Power reduction of chip multi-processors using shared resource control cooperating with dvfs. In Proceedings of the 27th International Conference on Computer Design, pages 615--622, October 2007.Google ScholarCross Ref
Index Terms
- Cooperative shared resource access control for low-power chip multiprocessors
Recommendations
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
ISVLSI '09: Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSINetworks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication ...
Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors
ICPP '10: Proceedings of the 2010 39th International Conference on Parallel ProcessingLimiting the peak power consumption of chip multiprocessors (CMPs) has recently received a lot of attention. In order to enable chip-level power capping, the peak power consumption of on-chip L2 caches in a CMP often needs to be constrained by ...
A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches
MEDEA '08: Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecturePower dissipation becomes an important issue in modern microprocessors such as chip multiprocessors (CMPs). Especially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the total power dissipation, thus ...
Comments