James R. Burnham
ABSTRACT
This paper describes a stochastic jitter model for analyzing the performance and bit error rate (BER) of digital timing recovery circuits. The model uses parallel interconnected Markov chains to simulate the behavior of the system in response to both random and deterministic jitter. Unlike conventional Markov-chain models that require the system to be stationary, the parallel-chain model approximates deterministic changes in conditions with transitions between sub-chains. To verify the accuracy of the model, an analysis was performed on a digital delay-locked loop, and the results compared to measured data. The resulting transition probabilities and BER predicted by the proposed model are more than three orders of magnitude more accurate than those predicted by a conventional Markov-chain model.
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Cross Ref
- A. N. Lokanathan and J. B. Brockman, "Efficient worst case analysis of integrated circuits," 1995 IEEE Custom Integrated Circuits Conference, pp. 237--240, May 1995.Google Scholar
- J. R. Burnham, Design and Analysis of jitter-tolerant digital delay-locked loops and fixed delay lines, Ph.D. Dissertation, Stanford University, June 2007.Google Scholar
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- M. Qi and G. P. Zhang, "Trend Time-Series Modeling and Forecasting With Neural Networks," 2008 IEEE Transactions on Neural Networks, vol. 19, no. 5, pp. 808--816, January 2008. Google ScholarDigital Library
Index Terms
- A stochastic jitter model for analyzing digital timing-recovery circuits
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