ABSTRACT
Existing 3D placement techniques are mainly used for standard-cell circuits, while mixed-size placement is needed to support high-level functional units and intellectual property (IP) blocks. In this paper we present an analytical 3D placement method that is capable of placing mixed-size circuits. A multiple-stepsize scheme for the analytical solver is proposed to handle standard cells and macros differently for stability and efficiency. To relieve the difficulty of legalization, 3D floorplan-based initial solutions are used to guide the analytical solver. As far as we know, this is the first work that reports 3D placement results for mixed-size circuits. Our experiments show that the multiple-stepsize scheme is better than single-stepsize schemes in both quality and runtime. The experimental results on the ICCAD'04 mixed-size benchmarks show that the 4-tier 3D mixed-size placement can reduce the wirelength by 27% on average compared to 2D placement. The results also show that the 3D mixed-size placement achieves 5.3% shorter wirelength on average than the pseudo 3D placement with similar amount of through-silicon vias (TS vias).
- S.N. Adya and I.L. Markov, "Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement," Proceedings of the 2002 International Symposium on Physical Design, pp. 12--17, 2002. Google ScholarDigital Library
- S.N. Adya, S. Chaturvedi, J.A. Roy, D.A. Papa, and I.L. Markov, "Unification of Partitioning, Placement and Floorplanning," Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, pp. 550--557, 2004. Google ScholarDigital Library
- C. Alpert, A. Kahng, G.-J. Nam, S. Reda, and P. Villarrubia, "A Semi-persistent Clustering Technique for VLSI Circuit Placement," Proceedings of the 2005 International Symposium on Physical Design, pp. 200--207, 2005. Google ScholarDigital Library
- K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, and A. Young, "Interconnects in the Third Dimension: Design Challenges for 3D ICs," Proceedings of the 44th Annual Conference on Design Automation, pp. 562--567, 2007. Google ScholarDigital Library
- T.F. Chan, J. Cong, and K. Sze, "Multilevel Generalized Force-directed Method for Circuit Placement," Proceedings of the 2005 International Symposium on Physical Design, pp. 185--192, 2005. Google ScholarDigital Library
- T.F. Chan, J. Cong, J.R. Shinnerl, K. Sze, and M. Xie, "mPL6: Enhancement Multilevel Mixed-Size Placement with Congestion Control," in Modern Circuit Placement, ed. G.-J. Nam and J. Cong, Springer Publishers, 2007.Google Scholar
- C. Chiang and S. Sinha, "The Road to 3D EDA Tool Readiness," Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pp. 429--436, 2009. Google ScholarDigital Library
- J. Cong and G. Luo, "A Multilevel Analytical Placement for 3D ICs," Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, pp. 361--366, 2009. Google ScholarDigital Library
- J. Cong and M. Xie, "A Robust Mixed-Size Legalization and Detailed Placement Algorithm," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1349--1362, August 2008. Google ScholarDigital Library
- J. Cong, G. Luo, J. Wei, and Y. Zhang, "Thermal-Aware 3D IC Placement Via Transformation," Proceedings of the 2007 Conference on Asia South Pacific Design Automation, pp. 780--785, 2007.Google Scholar
- J. Cong, G. Luo, and E. Radke, "Highly Efficient Gradient Computation for Density-Constrained Analytical Placement," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, no. 12, pp. 2133--2144, 2008. Google ScholarDigital Library
- J. Cong, J. Wei, and Y. Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," Proceedings of the 2004 IEEE/ACM International Conference on Computer-Aided Design, pp. 306--313, 2004. Google ScholarDigital Library
- W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, and P.D. Franzon, "Demystifying 3D ICs: The Pros and Cons of Going Vertical," IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498--510, 2005. Google ScholarDigital Library
- B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach," Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design, pp. 86, 2003. Google ScholarDigital Library
- B. Goplen and S. Spatnekar, "Placement of 3D ICs with Thermal and Interlayer Via Considerations," Proceedings of the 44th Annual Conference on Design Automation, pp. 626--631, 2007. Google ScholarDigital Library
- D. Hill, "Method and System for High Speed Detailed Placement of Cells within an Integrated Circuit Design," US Patent 6370673, April 9, 2002.Google Scholar
- G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: applications in VLSI domain," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 7, no. 1, pp. 69--79, 1999. Google ScholarDigital Library
- J. Nocedal and S.J. Wright, "Numerical Optimization 2nd ed.," Springer, 2006.Google Scholar
- H. Yan, Q. Zhou, and X. Hong, "Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm," Proceedings of the 9th International Symposium on Quality Electronic Design, pp. 289--292, 2008. Google ScholarDigital Library
- http://vlsicad.eecs.umich.edu/BK/ICCAD04bench/Google Scholar
Index Terms
- An analytical placer for mixed-size 3D placement
Recommendations
Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs
DAC '08: Proceedings of the 45th annual Design Automation ConferenceRoutability is a challenging cost metric for modern large-scale mixed-size placement. Most existing routability-driven placement algorithms apply whitespace allocation to relieve the routing congestion. Nevertheless, we observe that whitespace ...
Routability-driven placement for hierarchical mixed-size circuit designs
DAC '13: Proceedings of the 50th Annual Design Automation ConferenceA wirelength-driven placer without considering routability could introduce irresolvable routing-congested placements. Therefore, it is desirable to develop an effective routability-driven placer for modern mixed-size designs employing hierarchical ...
Combinatorial techniques for mixed-size placement
While recent literature on circuit layout addresses large-scale standard-cell placement, the authors typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of ...
Comments