Benjamin C. Lee
Engin Ipek
Doug Burger
Abstract
Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as dynamic random access memory (DRAM). In contrast, phase change memory (PCM) relies on programmable resistances, as well as scalable current and thermal mechanisms. To deploy PCM as a DRAM alternative and to exploit its scalability, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.
We propose architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6× slower and requires 2.2× more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2× and 1.0×, using narrow rows to mitigate write energy as well as multiple rows to improve locality and write coalescing. Partial writes mitigate limited memory endurance to provide more than 10 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.
- Aslot, V., Eigenmann, R. Quantitative performance analysis of the SPEC OMPM2001 benchmarks. Sci. Program. 11, 2 (2003). Google Scholar
Digital Library
- Bailey, D. et al. NAS parallel benchmarks. In Technical Report RNR-94-007, NASA Ames Research Center, March 1994.Google Scholar
- Bedeschi, F. et al. A multi-level-cell bipolar-selected phase-change memory. In International Solid-State Circuits Conference, 2008.Google ScholarCross Ref
- Chen, Y. et al. Ultra-thin phase-change bridge memory device using GeSb. In International Electron Devices Meeting, 2006.Google ScholarCross Ref
- Choi, Y. Under the hood: DRAM architectures: 8F2 vs. 6F2. EE Times, February 2008.Google Scholar
- Condit, J. et al. Better I/O through byte-addressable, persistent memory. In Symposium on Operating System Principles, Oct 2009. Google ScholarDigital Library
- Dong, X. et al. Leveraging 3D PCRAM technologies to reduce checkpoint overhead in future exascale systems. In Conference on Supercomputing, Nov 2009. Google ScholarDigital Library
- Horii, H. et al. A novel cell technology using N-doped GeSbTe films for phase change RAM. In Symposium on VLSI Technology, 2003.Google ScholarCross Ref
- Lai, S. Current status of the phase change memory and its future. In International Electron Devices Meeting, 2003.Google ScholarCross Ref
- Lee, B., Ipek, E., Mutlu, O., Burger, D. Architecting phase change memory as a scalable DRAM alternative. In International Symposium on Computer Architecture, June 2009. Google ScholarDigital Library
- Lee, K.-J. et al. A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput. J. Solid State Circuit. 43, 1 (Jan 2008).Google Scholar
- Micron. 512 Mb DDR2 SDRAM component data sheet: MT47H128M4B6-25. In www.micron.com, Mar 2006.Google Scholar
- Nirschl, T. et al. Write strategies for 2 and 4-bit multi-level phase-change memory. In International Electron Devices Meeting, 2008.Google Scholar
- Pirovano, A. et al. Scaling analysis of phase-change memory technology. In International Electron Devices Meeting, 2003.Google ScholarCross Ref
- Raoux, S. et al. Phase-change random access memory: A scalable technology. IBM J. Res. Dev. 52, 4/5 (Jul/Sept 2008). Google ScholarDigital Library
- Renau, J. et al. SESC simulator. In http://sesc.sourceforge.net, 2005.Google Scholar
- Semiconductor Industry Association. Process integration, devices & structures. International Technology Roadmap for Semiconductors, 2007.Google Scholar
- Sinha, M. et al. High-performance and low-voltage sense-amplifier techniques for sub-90 nm sram. In International Systems-on-Chip Conference, 2003.Google ScholarCross Ref
- Woo, S. et al. The SPLASH-2 programs: Characterization and methodological considerations. In International Symposium on Computer Architecture, June 1995. Google ScholarDigital Library
Index Terms
- Phase change memory architecture and the quest for scalability
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