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Bus-pin-aware bus-driven floorplanning

Published:16 May 2010Publication History

ABSTRACT

As the number of buses increase substantially in multi-core SoC designs, the bus planning problem has become the dominant factor in determining the performance and power consumption of SoC designs. To cope with the bus planning problem, it is desirable to consider this issue in early floorplanning stage. Recently, bus-driven floorplanning problem has attracted much attention in the literature. However, current algorithms adopt an over-simplified formulation ignoring the position and orientation of the bus pins may deteriorate the chip performance. In this paper, we propose the bus-driven floorplanning algorithm that fully considers the impacts of bus pins. By fully utilizing the position and orientation of bus pins, bus bendings are not restricted to occur at the modules on the bus that have more flexibilities in bus routing. With more flexibilities in the shapes of buses, the size of the solution space is increased and a better bus-driven floorplanning solution can be obtained. Compared with the state-of-the-art bus-driven floorplanner [5], the experimental results show that our algorithm performs better in runtime by 3.5x, success rate by 1.2x, wirelength by 1.8x, and reduced the deadspace by 1.2x.

References

  1. F. Rafiq, M. Chrzanowska-Jeske, H. H. Yang and N. Sherwani, "Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Microprocessor Designs," Proc. of ISPD, pp. 56--61, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
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  1. Bus-pin-aware bus-driven floorplanning

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      • Published in

        cover image ACM Conferences
        GLSVLSI '10: Proceedings of the 20th symposium on Great lakes symposium on VLSI
        May 2010
        502 pages
        ISBN:9781450300124
        DOI:10.1145/1785481

        Copyright © 2010 ACM

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 16 May 2010

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