skip to main content
10.1145/1837274.1837414acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis

Published:13 June 2010Publication History

ABSTRACT

Shrinking access cycle times and the employment of dynamic read/write assist circuits have made the use of standard static noise margins increasingly problematic for scaled SRAM designs. Recently proposed dynamic noise margins precisely characterize dynamic stability using the concept of stability boundaries, or separatrices, and provide elegant separatrix tracing algorithm. However, the present separatrix characterization method is only efficient in the two-dimensional state space and hence not practically applicable to fully extracted SRAM designs with additional parasitics. We present a rigorous system-theoretical approach for computing the tangent approximation to the separatrix in the high-dimensional space. Using this as a basis, we develop fast method based on tangent approximation and exact iterative-refinement method for analyzing SRAM dynamic stability. The proposed algorithms have been implemented as a SPICE-like CAD tool and are broadly applicable to efficient computation of dynamic noise margins.

References

  1. K. Chakraborty and P. Mazumder. Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories. Prentice Hall, 2002.Google ScholarGoogle Scholar
  2. International technology roadmap for semiconductors: Process integration, devices, and structures. 2007.Google ScholarGoogle Scholar
  3. J. Lohstroh, E. Seevinck, and J. D. Groot. Worst-case static noise margin criteria for logic circuits and their mathematical equivalence. IEEE J. of Solid-State Circuits, sc-18(6):803--806, Dec. 1983.Google ScholarGoogle Scholar
  4. E. Seevinck, F. J. List, and J. Lohstroh. Static-noise margin analysis of MOS SRAM cells. IEEE J. of Solid-State Circuits, sc-22(5):748--754, Oct. 1987.Google ScholarGoogle Scholar
  5. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl. The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. of Solid-State Circuits, 36(4):658--665, Apr. 2001.Google ScholarGoogle ScholarCross RefCross Ref
  6. R. V. Joshi, S. Mukhopadhyay, D. W. Plass, Y. H. Chan, C. Chuang, and A. Devgan. Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. In European Solid-State Circuits Conf., Sept. 2004.Google ScholarGoogle ScholarCross RefCross Ref
  7. E. Grossar, M. Stucchi, K. Maex, and W. Dehaene. Read stability and write-ability analysis of SRAM cells of nanometer technologies. IEEE J. of Solid-State Circuits, 41(11):2577--2588, Nov. 2006.Google ScholarGoogle ScholarCross RefCross Ref
  8. S. Mukhopadhyay, H. Mahmoodi, and K. Roy. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled cmos. IEEE Trans. CAD, 24(12):1859--1880, Dec. 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. K. Agarwal and S. Nassif. Statistical analysis of SRAM cell stability. In IEEE/ACM Design Automation Conf., July 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. R. Kanj, R. Joshi, and S. Nassif. Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. In IEEE/ACM Design Automation Conf., July 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. A. Singhee and R. A. Rutenbar. Statistical blockade: A novel method for very fast Monte Carlo simulation for rare circuit events, and its application. In IEEE/ACM Design, Automation and Test in Europe Conf., Apr. 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. S. Srivastava and J. Roychowdhury. Rapid estimation of the probability of SRAM failure due to MOS threshold variations. In IEEE Custom Integrated Circuits Conf., Sept. 2007.Google ScholarGoogle ScholarCross RefCross Ref
  13. H. Pilo et al. An SRAM design in 65nm and 45nm technology nodes featuring read and write-assist circuits to expand operating voltage. In Symp. on VLSI Circuits, June 2006.Google ScholarGoogle ScholarCross RefCross Ref
  14. M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb, and V. De. Wordline & bitline pulsing schemes for improving SRAM cell stability in low-vcc 65nm CMOS designs. In Symp. on VLSI Circuits, June 2006.Google ScholarGoogle Scholar
  15. W. Dong, P. Li, and G. M. Huang. Sram dynamic stability: Theory, variability and analysis. In IEEE/ACM Int. Conf. on CAD, Nov. 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. G. M. Huang, W. Dong, Y. Ho, and P. Li. Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch. In IEEE Int. Behavioral Modeling and Simulation Conf., 2007.Google ScholarGoogle ScholarCross RefCross Ref
  17. J. Zaborszky, G. M. Huang, B. Zheng, and T. C. Leung. On the phase portrait of a class of large nonlinear dynamic systems such as the power system. IEEE Trans. Automatic Control, pages 4--15, Jan. 1988.Google ScholarGoogle ScholarCross RefCross Ref
  18. W. Dong and P. Li. Final-value odes: stable numerical integration and its application to parallel circuit analysis. In IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. S. Wiggins. Introduction to Applied Nonlinear Dynamical Systems and Chaos. Springer, 2003.Google ScholarGoogle Scholar

Index Terms

  1. Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in
      • Published in

        cover image ACM Conferences
        DAC '10: Proceedings of the 47th Design Automation Conference
        June 2010
        1036 pages
        ISBN:9781450300025
        DOI:10.1145/1837274

        Copyright © 2010 ACM

        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 13 June 2010

        Permissions

        Request permissions about this article.

        Request Permissions

        Check for updates

        Qualifiers

        • research-article

        Acceptance Rates

        Overall Acceptance Rate1,770of5,499submissions,32%

        Upcoming Conference

        DAC '24
        61st ACM/IEEE Design Automation Conference
        June 23 - 27, 2024
        San Francisco , CA , USA

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader