Sandya S. Mannarswamy
ABSTRACT
Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs as an alternative to traditional lock based synchronization. However adoption of STM in mainstream software has been quite low due to its considerable overheads and its poor cache/memory performance. In this paper, we perform a detailed study of the cache behavior of STM applications and quantify the impact of different STM factors on the cache misses experienced by the applications. Based on our analysis, we propose a compiler driven Lock-Data Colocation (LDC), targeted at reducing the cache overheads on STM. We show that LDC is effective in improving the cache behavior of STM applications by reducing the dcache miss latency and improving execution time performance.
- }}C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In IISWC '08, pages 35--46, Sep 2008.Google Scholar
- }}Larus J., Rajwar R. Transactional Memory. Morgan and Claypool Publishers.Google Scholar
- }}D. Dice, O. Shalev N. Shavit. Transactional locking II. DISC 2004 Google ScholarDigital Library
Index Terms
- Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help
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