Abstract
Track assignment, which is an intermediate stage between global routing and detailed routing, provides a good platform for promoting performance, and for imposing additional constraints during routing, such as crosstalk. Gridless track assignment (GTA) has not been addressed in public literature. This work develops a gridless routing system integrating a congestion-driven global router, crosstalk-driven GTA and an enhanced implicit connection-graph-based router. Initial assignment is produced rapidly with a left-edge like algorithm. Crosstalk reduction on the assignment is then transformed to a restricted nonslicing floorplanning problem, and a deterministic O-Tree based algorithm is employed to reassign each net segment. Finally, each panel is partitioned into several subpanels, and the subpanels are reordered using branch and bound algorithm to decrease the crosstalk further. Before detailed routing, routing tree construction is undertaken for placed IRoutes and other pins; many original point-to-point routings are set to connect to IRoutes, and can be accomplished simply with pattern routing. For detailed routing, this work proposes a rapid extraction method for pseudomaximum stripped tiles to boost path propagation. Experimental results demonstrate that the proposed gridless routing system has over 2.02 times the runtime speedup in average for fixed- and variable-rule routings of an implicit connection-graph-based router, NEMO. As compared with a commercial routing tool, this work yields an average reduction rate of 13.8% in coupling capacitance calculated using its built-in coupling capacitance estimator.
- Batterywala, S., Shenoy, N., Nicholls, W., and Zhou, H. 2002. Track assignment: A desirable intermediate step between global routing and detailed routing. In Proceedings of the IEEE International Conference on Computer Aided Design. 59--66. Google ScholarDigital Library
- Chang, C. C. and Cong, J. 1999. An efficient approach to multilayer layer assignment with an approach to via minimization. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 18, 5, 608--620. Google ScholarDigital Library
- Chang, C. C. and Cong, J. 2001. Pseudopin assignment with crosstalk noise control. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 20, 5, 598--661. Google ScholarDigital Library
- Chang, Y. C., Chang, Y. W., Wu, G. M., and Wu, S. W. 2000. B*-trees: A new representation for non-slicing floorplans. In Proceedings of the ACM/IEEE Design Automation Conference, 458-463. Google ScholarDigital Library
- Cho, J. D., Raje, S., Sarrafzadeh, M., Sriram, M., and Kang, S. M. 1993. Crosstalk-minimum layer assignment. In Proceedings of the Custom Integrated Circuits Conference. 29.7.1--29.7.4.Google Scholar
- Cong, J., Fang, J., and Khoo, K. 2001. DUNE: A multilayer gridless routing system. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 20, 5, 633--646. Google ScholarDigital Library
- Dion, J. and Monier, L. M. 1995. Contour: A tile-based gridless router. Western Research Laboratory Res. rep. 95/3.Google Scholar
- Gao, T. and Liu, C. L. 1996. Minimum crosstalk channel routing. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 15, 5, 465--474. Google ScholarDigital Library
- Guo, P. N., Cheng, C. K., and Yoshimura, T. 2001. Floorplanning using a tree representation. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 20, 2, 281--289. Google ScholarDigital Library
- He, L. and Xu, M. 1999. Modeling and layout optimization for on-chip inductive coupling. Tech. rep. ECE-00-1. University of Wiscons in at Madison.Google Scholar
- Ho, T. Y., Chang, Y. W., Chen, S. J., and Lee, D. T. 2005. Crosstalk-and performance-driven multilevel full-chip routing. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 24, 6, 869--878. Google ScholarDigital Library
- Kao, W. C. and Parng, T. M. 1995. Cross point assignment with global rerouting for general-architecture designs. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 14, 3, 337--348. Google ScholarDigital Library
- Kastner, R., Bozogzadeh, E., and Sarrafzadeh, M. 2000. Predictable routing. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 110--113. Google ScholarDigital Library
- Kuo, Y. S., Chern, T. C., and Shih, W. K. 1988. Fast algorithm for optimal layer assignment. In Proceedings of the 25th ACM/IEEE Conference on Design Automation, 554--559. Google ScholarDigital Library
- Li, Y. L., Chen, X. Y., and Lin, Z. D. 2007. NEMO: A new implicit connection graph-based gridless router with multi-layer planes and pseudo-tile propagation. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 26, 4, 705--718. Google ScholarDigital Library
- Margarino, A., Romano, A., Gloria, A. De, Curatelli, F., and Antognetti, P. 1987. A tile-expansion router. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 6, 507--517.Google ScholarDigital Library
- Pan, M. and Chu, C. 2006. FastRoute: A step to integrate global routing into placement. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 464--471. Google ScholarDigital Library
- Sait, S. M. and Youssef, H. 1999. VLSI Physical Design Automation. World Scientific Publishing. Google ScholarDigital Library
- Sapatnekar, S. S. 2000. A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 19, 5, 550--559. Google ScholarDigital Library
- Shi, C. J. R. 1997. Solving constrained via minimization by compact linear programming. In Proceedings of the Asia and South Pacific Design Automation Conference. 635--640.Google ScholarCross Ref
- Tseng, H. P., Sheffer L., and Sechen, C. 2001. Timing- and crosstalk-driven area routing. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 20, 4, 528--544. Google ScholarDigital Library
- Tu, S. W., Shen, W. Z., Chang, Y. W., Chen, T. C., and Jou, J. Y. 2003. Inductance modeling for on-chip interconnects. Int. J. Analog Integr. Circ. Sig. Proce. 35, 1, 65--78. Google ScholarDigital Library
- Vittal, A. and Marek-Sadowska, M. 1997. Crosstalk reduction for VLSI. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 16, 4, 290--298. Google ScholarDigital Library
- Wu, D., Hu, J., Zhao, M., and Mahapatra, R. 2005. Timing driven track routing considering coupling capacitance. In Proceedings of the Asia and South Pacific Design Automation Conference. 1156--1159. Google ScholarDigital Library
- Xue, T., Kuh, E. S., and Wang, D. 1996. Post global routing crosstalk risk estimation and reduction. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 302--309. Google ScholarDigital Library
- Zhou, H. and Wong, D. F. 1999. Global routing with crosstalk constraint. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 18, 11, 1683--1688. Google ScholarDigital Library
Index Terms
- A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment
Recommendations
Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction
ISPD '08: Proceedings of the 2008 international symposium on Physical designTrack assignment, which is an intermediate stage between global routing and detailed routing, provides a good platform for promoting performance, and for imposing additional constraints during routing, such as crosstalk. Gridless track assignment (GTA) ...
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction
To handle modern routing with nanometer effects, we need to consider designs with variable wire/via widths and spacings, for which gridless-routing approaches are desirable due to its great flexibility. In this paper, we introduce a gridless-routing ...
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by ...
Comments