Joydip Das
Steven J.E. Wilton
ABSTRACT
We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and connection and switch block flexibilities, and the output is an estimate of the proportion of nets in a large circuit that can be expected to be routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. Together with the earlier works on analytical modeling, our model can be used to predict the routability without going through an expensive CAD flow. We show that the model correctly predicts routability trends.
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- An analytical model relating FPGA architecture parameters to routability
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