Peter Marwedel
Soonhoi Ha
ABSTRACT
The advent of embedded many-core architectures results in the need to come up with techniques for mapping embedded applications onto such architectures. This paper presents a representative set of such techniques. The techniques focus on optimizing performance, temperature distribution, reliability and fault tolerance for various models.
- Luca Benini, David Bertozzi, Bogliolo Alessandro, Francesco Menichelli, and Mauro Olivieri. MPARM: exploring the multi-processor SoC design space with SystemC. The Journal of VLSI Signal Processing, 41:169--182(14), 2005. Google Scholar
Digital Library
- B. Bouyssounouse. Home page of the ArtistDesign network of excellence. http://www.artist-embedded.org.Google Scholar
- Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, and Hiroaki Kunieda. MAPS: an integrated framework for MPSoC application parallelization. In 45th annual Design Automation Conference (DAC), pages 754--759, 2008. Google ScholarDigital Library
- Samarjit Chakraborty, Wolfgang Haid, Kai Huang, Simon Künzli, Alexander Maxiaguine, Simon Perathoner, Tobias Rein, Nikolay Stoimenov, Lothar Thiele, and Ernesto Wandeler. Modular performance analysis and real-time calculus. http://www.mpa.ethz.ch, 2009.Google Scholar
- Samarjit Chakraborty, Simon Künzli, and Lothar Thiele. A general framework for analyzing system properties in platform-based embedded system design. In Proc. Design, Automation and Test in Europe (DATE), pages 190--195, Munich, Germany, 2003. Google ScholarDigital Library
- A. Dasgupta and R. Karri. Electromigration reliability enhancement via bus activity distribution. Proc. DAC, pages 353--356, 1996. Google ScholarDigital Library
- R. P. Dick, D. L. Rhodes, and W. Wolf. TGFF: Task graphs for free. Proc. International Conference on Hardware/Software Codesign and System Synthesis (CODES), pages 97--101, 1998. Google ScholarDigital Library
- A. K. Goel. High-speed VLSI interconnections. IEEE Press, 2007. Google ScholarDigital Library
- Wolfgang Haid, Matthias Keller, Kai Huang, Iuliana Bacivarov, and Lothar Thiele. Generation and calibration of compositional performance analysis models for multi-processor systems. In Proc. Intl Conference on Systems, Architectures, Modeling and Simulation (SAMOS), pages 92--99, Samos, Greece, 2009. IEEE. Google ScholarDigital Library
- Kai Huang, Wolfgang Haid, Iuliana Bacivarov, Matthias Keller, and Lothar Thiele. Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications. ACM Transactions in Embedded Computing Systems (TECS), 2011. Google ScholarDigital Library
- L. Huang and Q. Xu. Agesim: A simulation framework for evaluating the lifetime reliability of processor-based socs. Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pages 51--56, 2010. Google ScholarDigital Library
- L. Huang and Q. Xu. Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint. Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pages 1584--1589, 2010. Google ScholarDigital Library
- L. Huang, R. Ye, and Q. Xu. Customer-aware task allocation and scheduling for multi-mode MPSoCs. Proc. ACM/IEEE Design Automation Conference (DAC), 2011. Google ScholarDigital Library
- L. Huang, F. Yuan, and Q. Xu. Lifetime reliability-aware task allocation and scheduling for MPSoC platforms. Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pages 51--56, 2009. Google ScholarDigital Library
- IBM. IBM PowerPC 750CL Microprocessor Revision Level DD2.x. http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/2F33B5691BBB8769872571D10065F7D5/$file/750cldd2x_ds_v2.4_pub_29May2007.pdf, 2007.Google Scholar
- Joint Electronic Device Engineering Councils (JEDEC). Jesdec85: Methods for calculating failure rates in units of fits. JEDEC Publication, 2001.Google Scholar
- Bart Kienhuis, Ed Deprettere, Kees Vissers, and Pieter van der Wolf. An approach for quantitative analysis of application-specific dataflow architectures. In Proc. of the Int'l Conference on Application-Specific Systems, Architectures and Processors (ASAP), pages 338--349, Washington, DC, USA, July 1997. Google ScholarDigital Library
- I. Koren and C. M. Krishna. Fault-tolerant systems. Morgan Kaufmann Publisher, 2007. Google ScholarDigital Library
- G. Kouveli, F. Hannig, J.-H. Lupp, and J. Teich. Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor. In Proceedings of the 3rd MARC Symposium, Ettlingen, Germany, July 2011. KIT Scientific Publishing.Google Scholar
- Jean-Yves Le Boudec and Patrick Thiran. Network calculus - a theory of deterministic queuing systems for the internet, volume 2050 of LNCS. Springer Verlag, Berlin, Germany, 2001. Google ScholarDigital Library
- E. A. Lee and D. G Messerschmitt. Synchronous data flow. Proceedings of the IEEE, 75:1235--1245, September 1987.Google ScholarCross Ref
- G. Manimaran and C. S. R. Murthy. A fault-tolerant dynamic scheduling algorithm for multiprocessor real-time systems and its analysis. IEEE Trans. Parallel and Distributed Systems, 9:1137--1152, November 1998. Google ScholarDigital Library
- P. Marwedel. Embedded system design. Springer, 2010. Google ScholarDigital Library
- P. Marwedel. Workshop on mapping of applications to MPSoCs. In http://www.artist-embedded.org/artist/Program,2298.html, 2011.Google Scholar
- T.G. Mattson, R.F. Van der Wijngaart, M. Riepen, T. Lehnig, P. Brett, W. Haas, P. Kennedy, J. Howard, S. Vangal, N. Borkar, G. Ruhl, and S. Dighe. The 48-core SCC processor: the programmer's view. In International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2010, Nov. 2010. Google ScholarDigital Library
- H. Nikolov, M. Thompson, T. Stefanov, A. Pimentel, S. Polstra, R. Bose, C. Zissulescu, and E. Deprettere. Daedalus: toward composable multimedia MP-SoC design. In 45th annual Design Automation Conference (DAC), pages 574--579, 2008. Google ScholarDigital Library
- Devendra Rai, Hoeseok Yang, Iuliana Bacivarov, Jian-Jia Chen, and Lothar Thiele. Worst-case temperature analysis for real-time systems. DATE11, Grenoble, France, 2011.Google ScholarCross Ref
- Tajana Simunic-Rosing, Ayse Kivilcim Coskun, and Keith Whisnant. Temperature aware task scheduling in MPSoCs. Design, Automation and Test in Europe (DATE), pages 1659--1664, 2007. Google ScholarDigital Library
- Kevin Skadron et al. Temperature-aware microarchitecture: modeling and implementation. ACM T. Arch. and Code Opt., 1(1):94--125, 2004. Google ScholarDigital Library
- J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. The case for lifetime reliability-aware microprocessors. Proc. International Symposium on Computer Architecture (ISCA), pages 276--287, 2004. Google ScholarDigital Library
- J. Teich. Invasive algorithms and architectures. it - Information Technology, 50(5):300--310, 2008.Google Scholar
- J. Teich, J. Henkel, A. Herkersdorf, D. Schmitt-Landsiedel, W. Schröder-Preikschat, and G. Snelting. Invasive Computing: An Overview. In Multiprocessor system-on-chip: hardware design and tool integration, pages 241--268. Springer, 2011.Google ScholarCross Ref
- Lother Thiele et al. Mapping applications to tiled multiprocessor embedded systems. In Proc. ACSD, pages 29--40, 2007. Google ScholarDigital Library
- Lothar Thiele, Lars Schor, Hoeseok Yang, and Iuliana Bacivarov. Thermal Aware system analysis ans software synthesis for embedded multi-processors. In Proc. Desicn Automation Conferene (DAC), San Diego, California, USA, 2011. ACM. Google ScholarDigital Library
- Ernesto Wandeler, Lothar Thiele, Marcel Verhoef, and Paul Lieverse. System architecture evaluation using modular performance analysis: a case study. Int'l Journal on Software Tools for Technology Transfer (STTT), 8(6):649--667, 2006. Google ScholarDigital Library
- D. Wentzlaff, P. Griffin, H. Hoffmann, Liewei Bao, B. Edwards, C. Ramey, M. Mattina, Chyi-Chang Miao, J. F. Brown, and A. Agarwal. On-chip interconnection architecture of the tile processor. Micro, IEEE, 27(5):15--31, Sept.-Oct. 2007. Google ScholarDigital Library
Index Terms
- Mapping of applications to MPSoCs
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