Kotb Jabeur
ABSTRACT
We present in this paper a circuit design approach to achieve compact logic circuits with ambipolar double-gate devices, using the in-field controllability of such devices. The approach is demonstrated for complementary static logic design style. We apply this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology and show that, with respect to conventional CMOS-like static logic structures and for comparable power consumption, time delay and integration density can both be improved by a factor of 1.5x and 2x, respectively. Compared with a predictive model for 16nm CMOS technology, the gates built according to the design approach described in this work and based on DG-CNTFET offer a gain of 30% concerning Power-Delay-Product (PDP).
- EDITION International Technology Roadmap for Semiconductors: Emerging Research Devices, 2009.Google Scholar
- S. Mukhopadhyay, et. al, "Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Devices and Circuits ISLPED, 2005 Google ScholarDigital Library
- L. Chang, et. al., "Direct tunneling gate leakage current in doublegate and ultrathin body MOSFETs", IEEE TED, vol. 49, Dec. 2002, pp. 2288--2295.Google ScholarCross Ref
- L. Mathew, et. al, "CMOS vertical multiple independent gate field effect transistors (MIGFET)", Int. SOI Conf., 2004, pp. 187--188.Google ScholarCross Ref
- J. Appenzeller et al"Dual-gate nanowire transistors with nickel silicide contacts", IEDM Technical Digest, 555--558 (2006).Google ScholarCross Ref
- Kotb Jabeur, Natalya Yakymets, Ian O'Connor and Sébastien Le Beux. "Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells", International Symposium on Nanoscale Architectures (NANOARCH), San Diego, June, 2011. Google ScholarDigital Library
- Ian O'Connor et al, "Double-Gate MOSFET based Reconfigurable Cells", Electronics Letters, vol 43, Nov. 2007.Google Scholar
- K.Roy et al, "Double-Gate SOI Devices for Low-Power and High-Performance Applications", VLSID'06. Google ScholarDigital Library
- Kotb. Jabeur et al, "Reducing transistor count in clocked standard cells with ambipolar double-gate FETs", IEEE/ACM international symposium on nanoscale architectures (Nanoarch'10), june 17-18 2010, Anaheim, CA,USA. Google ScholarDigital Library
- S. Frégonèse et al, "A Compact Model for Dual-Gate One Dimensional FET: Application toCarbon-Nanotube FETs", IEEE Trans. on Electron Devices, 58 (1), 206 (2011).Google ScholarCross Ref
- M. H. Ben Jamaa et al, "FPGA Design with Double-Gate Carbon Nanotube Transistors", ECS Transactions, 34 (1) 1005--1010 (2011)Google ScholarCross Ref
- L. Ding, A. Tselev, J. Wang, D. Yuan, H. Chu, T.P.McNicholas, Y. Li, J. Liu. "Selective Growth of Well-Aligned Semiconducting Single-Walled Carbon Nanotubes", Nano Letters, vol. 9, no. 2, pp. 800, 2009Google ScholarCross Ref
- A. Javey et al. "Self-Aligned Ballistic Molecular Transistors and Electrically Parallel Nanotube Arrays", Nano Letters, vol. 4, no. 7, pp. 1319--1322, 2004.Google ScholarCross Ref
- M. H. Ben Jamaa et al, "Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis", Design, Automation and Test in Europe (DATE). March 2009. Google ScholarDigital Library
- A. Raychowdhury et al, "Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance" in Proc. 3rd IEEE-NANO, 2003, vol. 2, pp. 343--346.Google Scholar
- J. Marulanda, et al, "Threshold and saturation voltages modeling of carbon nanotube field effect transistors (CNTFETs)", Nano, vol. 3, pp. 195--201, 2008.Google ScholarCross Ref
- J. Goguet et al, "A charge approach for a compact model of dual gate CNTFET" in Proc. Int. Conf. DTISNanoscale Era, 2008, pp. 1--5.Google Scholar
- Y. Lin et al, "High-performance carbon nanotube field-effect transistor with tunable polarities", IEEE Trans.Nanotechnol., vol. 4, no. 5, pp. 481--489, Sep. 2005. Google ScholarDigital Library
- A. Javey et al, "Carbon nanotube field-effect transistors with integrated ohmic contacts and high-k gate dielectrics," Nano Lett., vol. 4,no. 3, pp. 447--450, Mar. 2004.Google ScholarCross Ref
- http://ptm.asu.edu/modelcard/LP/16nm_LP.pmGoogle Scholar
- A. Javey, J. Guo, Q. Wang, M. Lundstrom, H. Dai, "Ballistic Carbon Nanotube Transistors". Nature, vol. 424, pp. 654--657, 2003.Google ScholarCross Ref
Index Terms
- Ambipolar double-gate FETs for the design of compact logic structures
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