Jacob Murray
ABSTRACT
Current commercial systems on chip (SoC) designs integrate an increasingly large number of pre-designed cores and their number is predicted to increase significantly in the near future. Specifically, molecular-scale computing will allow single or even multiple order-of-magnitude improvements in device densities. In the design of high-performance massive multi-core chips, power and temperature have become dominant constraints. Increased power consumption can raise chip temperature,which in turn can decrease chip reliability and performance and increase cooling costs.The new, ensuing possibilities in terms of single chip integration call for new paradigms, architectures, and infrastructures for high bandwidth and low-power interconnects. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links enable design of energy and thermally efficient sustainable multi-core platforms.
- Pande, P. et al. Sustainability through Massively Integrated Computing: Are We Ready to Break the Energy Efficiency Wall for Single-Chip Platforms? Proceedings of IEEE Design, Automation and Test in Europe (DATE), (Grenoble, FR, 2011), 1--6.Google Scholar
- Shang, L.,Peh, L.-S., Kumar, A. and Jha, N.K. Temperature-aware on-chip networks. IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, Jan.-Feb. 2006 Google ScholarDigital Library
- Ganguly, A. et al. Scalable Hybrid Wireless Network-on-Chip Architectures for Multi-Core Systems. IEEE Transactions on Computers, 60(10). 1485--1502. Google ScholarDigital Library
- Deb, S. et al.Enhancing Performance of Network-on-Chip Architectures with Millimeter-Wave Wireless Interconnects. Proceedings of IEEE International Conference on ASAP, (Rennes, Fr, 2010), 73--80.Google Scholar
- Marculescu, R. et al. Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 28(1). 3--21. Google ScholarDigital Library
- Ogras, U.Y. and Marculescu, R. It's a Small World After All: NoC Performance Optimization Via Long-Range Link Insertion. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(7). 693--706. Google ScholarDigital Library
- Chang, K. et al. Performance Evaluation and Design Trade-Offs for Wireless Network-on-Chip Architectures.ACM Journal on Emerging Technologies in Computing Systems Google ScholarDigital Library
- Zhao, D. and Wang, Y., SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip. IEEE Transactions on Computers, 57(9). 1230--1245 Google ScholarDigital Library
- Lee, B.G.et al. Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks. IEEE Photonics Technology Letters, 20(6). 398--400.Google ScholarCross Ref
- Woo, S.C. et al. The SPLASH-2 Programs: Characterization and Methodological Considerations. Proceedings of Annual International Symposium on Computer Architecture, (Santa MargheritaLigure, IT, 1995), 24--36. Google ScholarDigital Library
- Binkert, N. et al. The GEM5 Simulator. ACM SIGARCH Computer Architecture News, 39(2). 1--7. Google ScholarDigital Library
- Skadron, K. et al. Temperature-Aware Microarchitecture. Proceedings of the International Symposium on Computer Architecture, (2003), 2--13. Google ScholarDigital Library
Index Terms
- Sustainable multi-core architecture with on-chip wireless links
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