ABSTRACT
Phase-Change Memory (PCM) is emerging as a promising new memory technology, due to its inherent ability to scale deeply into the nanoscale regime. However, PCM is still marred by a duet of potentially show-stopping deficiencies: poor write performance and limited durability. These weaknesses have urged designers to develop various supporting architectural techniques to aid and complement the operation of the PCM, while mitigating its innate flaws. One promising such solution is the deployment of hybridized memory architectures that fuse DRAM and PCM, in order to combine the best attributes of each technology. In this paper, we introduce a Dual-Phase Compression (DPC) scheme specifically optimized for DRAM/PCM hybrid environments. Extensive simulations with traces from real applications running on a full-system simulator of a multicore system demonstrate 35.1% performance improvement and 29.3% energy reduction, on average, as compared to a baseline DRAM/PCM hybrid implementation.
- A. R. Alameldeen and D. A. Wood. Adaptive cache compression for high-performance processors. In Proceedings of the ISCA 2004. Google ScholarDigital Library
- A. R. Alameldeen and D. A. Wood. Frequent pattern compression: A significance-based compression scheme for l2 caches. In Technical Report 1500, Computer Sciences Department, University of Wisconsin-Madison, April 2004.Google Scholar
- R. Bagrodia and et al. Parsec: A parallel simulation environment for complex systems. Computer, 31:77--85, October 1998. Google ScholarDigital Library
- A. Bivens and et al. Architectural design for next generation heterogeneous memory systems. IEEE International Memory Workshop, pages 1 -- 4, May 2010.Google ScholarCross Ref
- S. Cho and H. Lee. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the MICRO 2009. Google ScholarDigital Library
- R. Das and et al. Performance and power optimization through data compression in network-on-chip architectures. Proceedings of the HPCA 2008, pages 215 -- 225.Google Scholar
- G. Dhiman, R. Ayoub, and T. Rosing. PDRAM: a hybrid PRAM and DRAM main memory system. In Proceedings of the DAC 2009, pages 664--469. Google ScholarDigital Library
- A. P. Ferreira and et al. Using PCM in next-generation embedded space applications. Proceedings of the RTAS 2010. Google ScholarDigital Library
- R. F. Freitas and W. W. Wilcke. Storage-class memory: The next storage system technology. IBM Journal of Research and Development, 52(4/5):439 -- 447, 2008. Google ScholarDigital Library
- HP Labs. CACTI: an integrated cache and memory access time, cycle time, area, leakage and dynamic power model. http://www.hpl.hp.com/research/cacti/.Google Scholar
- H. Jung and et al. A 58nm 1.8v 1Gb PRAM with 6.4MB/s program BW. In Proceedings of IEEE ISSCC 2011.Google Scholar
- S. Kang and et al. A 0.1/spl mu/m 1.8V 256Mb 66MHz synchronous burst PRAM. In Proceedings of the ISSCC 2006, pages 487 -- 496.Google Scholar
- J. Kong and H. Zhou. Improving privacy and lifetime of PCM-based main memory. In Proceedings of the DSN 2010.Google Scholar
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the ISCA 2009, pages 2--13. Google ScholarDigital Library
- P. S. Magnusson and et al. Simics: A full system simulation platform. Computer, 35:50--58, February 2002. Google ScholarDigital Library
- M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the ISCA 2009. Google ScholarDigital Library
- Samsung Electronics. DDR2 registered SDRAM module, M393T5160QZA. Datasheet.Google Scholar
- G. Sun, D. Niu, J. Ouyang, and Y. Xie. A frequent-value based pram memory architecture. In Proceedings of the ASP-DAC 2011, pages 211--216. Google ScholarDigital Library
- J. Yang, Y. Zhang, and R. Gupta. Frequent value compression in data caches. In Proceedings of the MICRO 2000, pages 258--265. Google ScholarDigital Library
- W. Zhang and T. Li. Characterizing and mitigating the impact of process variations on phase changed based memory systems. In Proceedings of the MICRO 2009. Google ScholarDigital Library
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In Proceedings of the ISCA 2009, pages 14--23. Google ScholarDigital Library
Index Terms
- A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures
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