ABSTRACT
An instruction scheduling technique is presented that targets at improving the reliability of a software program given a user-provided tolerable performance overhead. A look-ahead-based heuristic schedules instructions by evaluating the reliability of dependent instructions while reducing the impact of spatial and temporal vulnerabilities of various processor components. Our reliability-driven instruction scheduler (implemented into the GCC compiler) provides on average a 22% reduction of program failures compared to state-of-the-art.
- R. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE TDMR, vol. 5, no. 3, pp. 305--316, 2005.Google Scholar
- P. Shivakumar, M. Kistler, "Modeling the effect of technology trends on the soft error rate of combinational logic". IEEE DSN, vol. 47, no. 6, pp. 2586--2594, 2002.Google Scholar
- R. Vadlamani, J. Zhao, W. Burleson, R. Tessier, "Multicore soft error rate stabilization using adaptive dual modular redundancy", DATE, pp. 27--32, 2010. Google ScholarDigital Library
- D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, K. Flautner, "Razor: circuit-level correction of timing errors for low-power operation," IEEE MICRO, vol. 24, no. 3, pp. 10--20, 2004. Google ScholarDigital Library
- S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, T. Austin, "A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor", MICRO, pp. 29--40, 2003. Google ScholarDigital Library
- R. Venkatasubramanianw, J. P. Hayes, B. T. Murray, "Low cost online fault detection using control flow assertions". IEEE IOLTS, pp. 137--143, 2003.Google ScholarCross Ref
- P. P. Shirvani, N. R. Saxena, E. J. McCluskey, "Software implemented EDAC protection against SEUs". IEEE Transactions on Reliability, vol 49, pp. 273--284, 2000.Google ScholarCross Ref
- V. Sridharan, "Introducing Abstraction to Vulnerability Analysis", Ph.D. Thesis, March 2010.Google Scholar
- J. Hu, S. Wang, S. G. Ziavras, "In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability," DSN, pp. 281--290, 2006. Google ScholarDigital Library
- J. S. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, "Compiler-Directed Instruction Duplication for Soft Error Detection," DATE, vol. 2, pp. 1056--1057, 2005 Google ScholarDigital Library
- J. Yan, W. Zhang, "Compiler guided register reliability improvement against soft errors," IEEE EMSOFT, pp. 203--209, 2005. Google ScholarDigital Library
- X. Fu, W. Zhang, T. Li, J. Fortes, "Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures", International Conference on Parallel Processing, pp. 190--197, 2008. Google ScholarDigital Library
- J. Gaisler, "A portable and fault-tolerant microprocessor based on the SPARC v8 architecture", DSN, pp. 409--415, 2002. Google ScholarDigital Library
- Flux calculator: www.seutest.com/cgi-bin/FluxCalculator.cgi.Google Scholar
- IBM® XIV® Storage System cache: http://publib.boulder.ibm.com/infocenter/ibmxiv/r2/index.jsp.Google Scholar
- AMD PhenomTM II Processor Product Data Sheet 2010.Google Scholar
- G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, D. I. August, S. S. Mukherjee, "Software controlled fault tolerance," ACM TACO, vol. 2, pp. 366--396, 2005. Google ScholarDigital Library
- T. Ball, J. R. Larus, "Branch Prediction for Free", ACM SIGPLAN, vol. 28, pp. 300--313, 1993. Google ScholarDigital Library
- J. Xu, Q. Tan, R. Shen, "The Instruction Scheduling for Soft Errors based on Data Flow Analysis", IEEE Pacific Rim International Symposium on Dependable Computing, pp. 372--378, 2009. Google ScholarDigital Library
- A. Benso, S. Chiusano, P. Prinetto, L. Tagliaferri, "A C/C++ Source-to-Source Compiler for Dependable Applications", DSN, pp. 71--78, 2000. Google ScholarDigital Library
- M. Shafique, L. Bauer, J. Henkel, "Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms", JSPS, vol. 60, no. 2, pp. 183--210, 2010. Google ScholarDigital Library
- A. Parikh, S. Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, "Instruction scheduling for low-power", Journal of VLSI Signal Processing systems, vol 37, no. 1, pp. 129--149, 2004. Google ScholarDigital Library
- S. Rehman, M. Shafique, F. Kriebel, J. Henkel, "Reliable software for unreliable hardware: Embedded code generation aiming at reliability", Codess+ISSS, pp. 237--246, 2011. Google ScholarDigital Library
- S. Rehman, M. Shafique, F. Kriebel, J. Henkel, "RAISE: Reliability-Aware Instruction SchEduling for Unreliable Hardware", ASP-DAC, pp. 671--676, 2012.Google Scholar
- M. Shafique, B. Zatt, S. Rehman, F. Kriebel, J. Henkel, "Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding", IEEE DATE, pp. 697--702, 2012.Google Scholar
- S. Rehman, M. Shafique, F. Kriebel, J. Henkel, "ReVC: Computationally Reliable Video Coding on Unreliable Hardware Platforms: A Case Study on Error-Tolerant H.264/AVC CAVLC Entropy Coding", IEEE ICIP, pp. 405--408, 2011.Google ScholarCross Ref
- Haifa Scheduler: http://gcc.gnu.org/, http://opensource.apple.com/source/gcc_os/gcc_os-1660/gcc/haifa-sched.cGoogle Scholar
Index Terms
- Instruction scheduling for reliability-aware compilation
Recommendations
Reliable software for unreliable hardware: embedded code generation aiming at reliability
CODES+ISSS '11: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesisA compilation technique for reliability-aware software transformations is presented. An instruction-level reliability estimation technique quantifies the effects of hardware-level faults at the instruction-level while considering spatial and temporal ...
Fast, frequency-based, integrated register allocation and instruction scheduling
Instruction scheduling and register allocation are two of the most important optimization phases in modern compilers as they have a significant impact on the quality of the generated code. Unfortunately, the objectives of these two optimizations are in ...
Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures
In this paper, we address the problem of generating an optimal instruction sequence S for a Directed Acyclic Graph (DAG), where S is optimal in terms of the number of registers used. We call this the Minimum Register Instruction Sequence (MRIS) problem. ...
Comments