Sung Kyu Park
ABSTRACT
We propose a novel wear-leveling algorithm for the hybrid main memory architecture which exploits both fast read and write speed of DRAM and low power consumption and high density of PRAM. The wear-leveling algorithm consists of three techniques: DRAM buffering for reducing the write count, multiple data swapping for evening out the write count among all pages, and data shifting evening out the write count among all pages and lines. In order to evaluate performance, we implement a PIN-based wear-leveling simulator. In SPEC CPU2006, our proposed schemes can reduce the write count and maintain the write count equally among all pages and lines with little additional overhead.
- P. Zhou, B. Zhao, J. Yang, and Y. Zhang, A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology, Proc. The 36th International Symposium on Computer Architecture (ISCA '09), pp. 14--23, 2009. Google Scholar
Digital Library
- Y. Park, S.-H. Lim, C. Lee, and K. H. Park, PFFS: A Scalable Flash Memory File System for the Hybrid Architecture of Phase-Change RAM and NAND Flash, Proc. The 2008 ACM Symposisum on Applied Computing (SAC '08), pp. 1498--1503, 2008. Google ScholarDigital Library
- M. K. Qureshi, V. Srinivasan, and J. A. Rivers, Scalable High Performance Main Memory System Using Phase-Change Memory Technology, Proc. The 36th International Symposium on Computer Architecture (ISCA '09), pp. 24--33, 2009. Google ScholarDigital Library
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