Renu Mehra
ABSTRACT
Low-power EDA has come a long way in from its infancy almost 20 years ago, when the first low power tools for logic synthesis were introduced. Currently a large number of power-aware tools provide a spectrum of capabilities to address power issues, from analysis of power consumption and IR drops to automated power reduction during chip implementation. The most recent development is the advent of standards to specify power intent along with RTL which resulted in a number of new tools to help users implement and verify their power intent.
This paper takes a look at the different techniques that are commercially available to analyze, optimize, and manage the power consumption of modern day chips. The purpose is not to evaluate the different tools, but to provide an overview of the capabilities available commercially. Since it is impossible to do justice to all the tools that provide low power capabilities in this short space, I focus on a few representative tools. The scope is limited to tools for digital design starting from RTL.
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Index Terms
- Commercial low-power EDA tools: a review
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