Sae Kyu Lee
ABSTRACT
This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" logic blocks on top of each other, voltage stacking reduces the chip current draw and simplifies off-chip power delivery but within-die voltage noise due to inter-layer current mismatch is an issue. Results show that unlike conventional power delivery schemes, supply rail impedance in voltage stacked systems depend on aggregate power consumption, leading to better noise immunity for high power (low impedance) operation for many-core processors.
- E. Alon and M. Horowitz. Integrated regulation for energy-efficient digital circuits. IEEE J. Solid-State Circuits, 43(8):1795--1807, August 2008.Google Scholar
Cross Ref
- L. Chang, R. K. Montoye, B. L. Ji, A. J. Weger, K. G. Stawiasz, and R. H. Dennard. A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2. IEEE Symp. VLSI Circuits, pages 55--56, June 2010.Google Scholar
- R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. Near-threshold computing: reclaiming Moore's law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2):253--266, February 2010.Google ScholarCross Ref
- H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger. Dark silicon and the end of multicore scaling. Proc. 38th Int'l Symp. Computer Architecture, ACM Press, pages 365--376, June 2011. Google ScholarDigital Library
- W. Kim, D. Brooks, and G.-Y. Wei. A fully-integrated 3-level dc/dc converter for nanosecond-scale dvs with fast shunt regulation. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pages 268--270, February 2011.Google ScholarCross Ref
- M. Nagata, T. Okumoto, and K. Taki. A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. IEEE J. Solid-State Circuits, 40(4):813--819, April 2005.Google ScholarCross Ref
- L. S. Nielsen, C. Niessen, J. Sparso, and K. van Berkel. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage. IEEE Transactions on VLSI Systems, 2(4):391--397, 1994. Google ScholarDigital Library
- S. Rajapandian, K. L. Shepard, P. Hazucha, and T. Karnik. High-voltage power delivery through charge recycling. IEEE J. Solid-State Circuits, 41(6):1400--1410, June 2006.Google ScholarCross Ref
Index Terms
- Evaluation of voltage stacking for near-threshold multicore computing
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