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A locality-aware bi-level mesh-mesh 2d-noc architecture for future thousand core CMPs

Published:03 June 2012Publication History

ABSTRACT

The scalability of the flat-mesh network-on-chip (NoC) architecture is limited due to the increase in the network diameter. In this work, a locality-aware bi-level mesh-mesh network architecture is proposed to balance the number of packets injected between the top and bottom level networks, without placing any constraints on the destination nodes. The results of the network analysis for a 1024 core CMP demonstrate an increase of upto ≈ 34% in the throughput compared to a flat-mesh, while consuming upto ≈ 10% less energy per flit. In comparison to a hierarchical CMesh NoC topology, the proposed network provides upto 2.5 X improvement in the throughput while consuming approximately the same amount of energy per flit. Similar results of higher throughput and low energy compared to the flat-mesh and CMesh NoC topologies are observed down to smaller 100-core CMPs.

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  • Published in

    cover image ACM Conferences
    SLIP '12: Proceedings of the International Workshop on System Level Interconnect Prediction
    June 2012
    58 pages
    ISBN:9781450314374
    DOI:10.1145/2347655

    Copyright © 2012 Authors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 3 June 2012

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    Overall Acceptance Rate6of8submissions,75%
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