ABSTRACT
Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal registers, it is imperative to minimize the total retention storage size. The current industry practice only replace all registers with single-bit retention ones, which significantly limits the design freedom and results in excessive area and power overhead. Towards this, for the first time in literature, we propose the concept of multi-bit retention register, with which only selected registers need to be replaced. It can significantly reduce the number of bits that need to be stored and thus the area and leakage power, but needs several clock cycles for mode transition. In addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode and the retention storage area by 66.03%, compared with the single-bit retention register based design.
- P. Ashar, and S. Malik, "Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications", in Proc. Design Automation Conference, DAC, 1994, pp77--80 Google ScholarDigital Library
- E. Choi, C. Shin, T. Kim, and Y. Shin, "Power-Gating-Aware High-Level Synthesis", in Proc. Low Power Electronics and Design (ISLPED), 2008, pp. 39--44. Google ScholarDigital Library
- A. Darbari, B. M. Al-Hashimi, D. Flynn, and J. Biggs, "Selective State Retention Design using Symbolic Simulation" in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2009, pp. 1644--1649. Google ScholarDigital Library
- Mahmoodi-Meimand, H. and Roy, K, "Data-Retention Flip-Flops for Power-Down Applications", in Proc. IEEE Symposium on Circuit and System (ISCAS), 2004, pp. II - 677--80 Vol. 2Google Scholar
- H. Jiang, M. Marek-Sadowska, S. R. Nassif, "Benefits and costs of power-gating technique", in Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), 2005, pp. 559--566. Google ScholarDigital Library
- H. Jiao and V. Kursun, "High-Speed and Low-Leakage MTCMOS Memory Registers" in Proc. Quality Electronic Design (ASQED), 2010, pp. 17--22.Google ScholarCross Ref
- M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual, For System-on-Chip Design, Springer, 2007. Google ScholarDigital Library
- H.-O. Kim and Y. Shin, "Semicustom design methodology of power gated circuits for low leakage applications," IEEE TCAS II, vol. 54, no. 6, June 2007, pp. 512--516.Google Scholar
- J. Seomun and Y. Shin, "Self-Retention of Data in Power-Gated Design", in Proc. SoC Design Conference (ISOCC), 2009, pp. 212--215.Google Scholar
- S. Yang, B. M. Al-Hashimi, D. Flynn, and S. Khursheed, "Scan Based Methodology for Reliable State Retention Power Gating Design", in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, pp. 69--74. Google ScholarDigital Library
Index Terms
- Efficient multiple-bit retention register assignment for power gated design: concept and algorithms
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