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FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only)

Published:11 February 2013Publication History

ABSTRACT

Support Vector Machines (SVMs) are considered one of the most popular classification algorithms yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, and hence it is challenging to meet real-time processing constraints imposed by many embedded applications. In order to improve SVM classification times the cascade classification scheme has been proposed. However, even in this case real-time performance is still challenging to achieve without exploiting the throughput and processing requirements of each cascade stage. Hence the design of an FPGA-based accelerator for cascaded SVM processing is proposed; in addition to a hardware reduction method in order to reduce the implementation requirements of the cascade SVM leading to significant resource savings. The accelerator was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. It was compared against FPGA implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The accelerator is capable an average performance of 70 frames-per-second, achieving a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less FPGA LUT resources, with only 0.7% reduction in classification accuracy.

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  1. FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only)

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        • Published in

          cover image ACM Conferences
          FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
          February 2013
          294 pages
          ISBN:9781450318877
          DOI:10.1145/2435264

          Copyright © 2013 Authors

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          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 11 February 2013

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