ABSTRACT
Support Vector Machines (SVMs) are considered one of the most popular classification algorithms yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, and hence it is challenging to meet real-time processing constraints imposed by many embedded applications. In order to improve SVM classification times the cascade classification scheme has been proposed. However, even in this case real-time performance is still challenging to achieve without exploiting the throughput and processing requirements of each cascade stage. Hence the design of an FPGA-based accelerator for cascaded SVM processing is proposed; in addition to a hardware reduction method in order to reduce the implementation requirements of the cascade SVM leading to significant resource savings. The accelerator was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. It was compared against FPGA implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The accelerator is capable an average performance of 70 frames-per-second, achieving a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less FPGA LUT resources, with only 0.7% reduction in classification accuracy.
Index Terms
FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only)
Recommendations
A hardware-efficient architecture for embedded real-time cascaded support vector machines classification
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIThis work presents an optimized architecture for cascaded SVM processing, along with a hardware reduction method for the implementation of the additional stages in the cascade, leading to significant improvements. The architecture was implemented on a ...
A Classification Processor for a Support Vector Machine with Embedded DSP Slices and Block RAMs in the FPGA
MCSOC '13: Proceedings of the 2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-ChipThis paper presents an FPGA implementation of a Support Vector Machine (SVM) classification using the DSP slices and block RAMs in the Xilinx Virtex-6 family FPGA. In our approach, the SVM classification is performed by the multiple DSPs. Our ...
A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines
FCCM '09: Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing MachinesWe present a massively parallel FPGA-based coprocessor for Support Vector Machines (SVMs), a machine learning algorithm whose applications include recognition tasks such as learning scenes, situations and concepts, and reasoning tasks such as analyzing ...
Comments