Gerhard Fuchs
ABSTRACT
I present preliminary results of my work on an architecture for Wireless Sensor Networks (nets) that realizes the novel concept of ASFECs (approximately synchronized fetch-and-execute cycles). This architecture extends the classical fetch-and-execute cycles of computers by syncing phases. It guarantees a consistent value of the instruction pointer for all (sensor) nodes and a maximum skew between the starting times of the corresponding instructions on the nodes. In addition, I present my current work. I show how ASFECs can process net-assemblies. So far, I have studied centralized nets, only. I expect that ASFECs can be a important step towards fully deterministic, hard real time measurements fulfilled by nets.
- R. Flury and R. Wattenhofer. Slotted Programming for Sensor Networks. In Proc. of the 9th ACM/IEEE Int. Conf. on Information Processing in Sensor Networks, pages 24--34. ACM, 2010. (IPSN: Stockholm, SE-AB; Apr. 2010). Google Scholar
Digital Library
- LAN/MAN Standards Committee. IEEE Standard for Local and metropolitan area networks - Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs). IEEE Std 802.15.4#8482;-2011, IEEE Computer Society, June 2011.Google Scholar
- K. Römer, P. Blum, and L. Meier. Time Synchronization and Calibration in Wireless Sensor Networks. In I. Stojmenovic, editor, Handbook of Sensor Networks: Algorithms and Architectures, pages 199--238. John Wiley & Sons, Hoboken, US-NJ, 2005.Google ScholarCross Ref
Index Terms
- Poster abstract: ASFECs: using approximately synchronized fetch-and-execute cycles as basic operation cycles for wireless sensor networks
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