Uwe Deidersen
ABSTRACT
Multiple-input multiple-output (MIMO) wireless transmission together with iterative decoding at the receiver is a key technique to achieve high spectral efficiency. However, particularly the required soft-input soft-output (SISO) MIMO detector entails a very high complexity, which motivates the investigation of suboptimal detectors with reduced complexity. In this paper, we present-to the best of our knowledge-the first implementation of a parallel VLSI architecture for a SISO detector based on Markov chain Monte Carlo (MCMC) methods. The proposed architecture is scalable and allows to exploit the parallelism inherent in the considered MCMC algorithm. We investigate the implementation costs and show that this architecture covers a wide range of trade-offs between throughput and silicon area.
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Cross Ref
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Index Terms
- A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detection
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