Dong Yazhuo
ABSTRACT
There are large numbers of high-level algorithms consisting of multiple loop nests in image compression, pattern recognition and digital signal processing. FPGA provides a convenient and flexible solution to speed up these loop-intensive algorithms. However, FPGA reconfiguration which needs a long time is inevitable when switching between the loop nests. This paper presents a parameterized pipeline template to execute all the loop nests in sequence without FPGA reconfiguration. Five steps are designed to decide the parameters. Experiments show that the pipeline template can achieve a comparative execution cycles for a loop comparing with the special hardware structure.
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Digital Library
- Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivara-man, "PICO: Automatically Designing Custom Computers." IEEE Computer 35(9), pp. 39--47, 2002. Google ScholarDigital Library
Index Terms
- Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources
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