Stefano Frache
Abstract
Density and regularity are deemed as the major advantages of nanoarray architectures based on nanowires. Literature demonstrated that proper reliability analyzes must be performed and solutions have to be devised to improve nanoarrays yield. Their complexity and high-fault probability claim for specific design automation tools able to explore circuit solutions, performance and fault-tolerant approaches.
We envision a simulator conceived to carry on characterizations in terms of logic behavior, defect-induced output error rate assessment, switching activity, power and timing performance. Though already existing for traditional technology, a simulator based on specific technological and topological tiled nanoarray descriptions, and conceived to join both device and architecture levels, has never been attempted at the degree of accuracy we present.
Our contribution is twofold. First, marking a difference with respect to the state of the art, we developed an algorithm based on an event-driven engine which works at switch level and is not simply built on top of cost functions evaluations. The straightforward advantage is the possibility to follow the evolution of dynamic control sequences throughout all the inner components of the nanoarray, and, as a consequence, to obtain circuit level characterization as a projection of the real internal parameters.
Second, we added to our simulator the capability to inject faults with specific statistical distributions associated to the nanoarray topology. Here we extract output error rates and yield for one of the possible nanoarray structures proposed in literature, the NASIC. Results specificity and accuracy demonstrate the simulator trustworthiness, its effectiveness for extensive nanoarrays characterization and its suitability as a foundation for both higher architectural and lower device simulation levels.
The aim of this work, then, is to provide insights into the intertwined relation between actual technology and circuit design for these emerging fabrics, and, as a consequence, to clarify how defects and variability affect circuits and systems performance.
- Ahn, S., Patitz, Z., Park, N., Kim, H. J., and Park, N. 2009. A floorprint-based defect tolerance for nano-scale application-specific IC. IEEE Trans. Instrum. Measure. 58, 5, 1283--1290.Google Scholar
Cross Ref
- Angiolini, F., Jamaa, M., Atienza, D., Benini, L., and De Micheli, G. 2007. Improving the fault tolerance of nanometric PLA designs. In Proceedings of the Design, Automation Test in Europe Conference Exhibition, 2007 (DATE'07). 1--6. Google ScholarDigital Library
- Awais, M., Vacca, M., Graziano, M., and Masera, G. 2012. Fft implementation using QCA. In Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Seville, Spain. IEEE, 741--744.Google Scholar
- Awais, M., Vacca, M., Graziano, M., Ruo Roch, M., and Masera, G. 2013. Quantum dot Cellular automata check node implementation for ldpc decoders. IEEE Trans. Nanotech. 99, 10.Google Scholar
- Bhaduri, D. and Shukla, S. 2004. Nanolab: A tool for evaluating reliability of defect-tolerant nano architectures. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. 25--31. Google ScholarDigital Library
- Chiolerio, A., Allia, P., and Graziano, M. 2012. Magnetic dipolar coupling and collective effects for binary information codification in cost-effective logic devices. J. Magnet. Magnetic Mat. 324, 7.Google ScholarCross Ref
- Compaño, R., Molenkamp, L., and Paul, D. J. 2000. Technology roadmap for nanoelectronics. European Commission, Microelectronics Advanced Research Initiative MEL-ARI NANO, http://www.cordis.ln/esprit/src/melari/.htm.Google Scholar
- Crepaldi, M., Rattalino, I., Motto, P., Demarchi, D., and Civera, P. 2013. A 0.13 murmm CMOS operational schmitt trigger r-to-f converter for nanogap-based nanosensors read-out. IEEE Trans. Circ. Syst. I: Regular Papers, 60, 4, 975--988.Google ScholarCross Ref
- Dehon, A. 2002. Array based architectures for molecular electronics. In Proceedings of the 1st Workshop on Non-Silicon Computations (NSC-1).Google Scholar
- DeHon, A. 2005. Nanowire-based programmable architectures. J. Emerg. Technol. Comput. Syst. 1, 2, 109--162. Google ScholarDigital Library
- Dezan, C., Teodorov, C., Lagadec, L., Leuchtenburg, M., Wang, T., Narayanan, P., and Moritz, A. 2009. Towards a framework for designing applications onto hybrid nano/cmos fabrics. Microelectron. J. 40, 45, 656--664. Google ScholarDigital Library
- Frache, S., Chiabrando, D., Graziano, M., Riente, F., Turvani, G., and Zamboni, M. 2012. Topolinano: Nanoarchitectures design made real. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (Amsterdam, The Netherlands). IEEE, 160--167.Google Scholar
- Frache, S., Graziano, M., and Zamboni, M. 2010. A flexible simulation methodology and tool for nanoarray-based architectures. In Proceedings of the 28th IEEE International Conference on Computer Design (ICCD 2010) (Amsterdam, The Netherlands). IEEE, 60--67.Google Scholar
- Graziano, M., Chiolerio, A., and Zamboni, M. 2009. A technology aware magnetic QCA NCL-HDL architecture. In Proceedings of the International Conference on Nanotechnology (Genova, Italy). 763--766.Google Scholar
- Graziano, M., Frache, S., and Zamboni, M. 2013. A hardware viewpoint on biosequence analysis: What's next? J. Emerg. Technol. Comput. Syst. 9, 4, Article 29. Google ScholarDigital Library
- Graziano, M., Vacca, M., Blua, D., and Zamboni, M. 2011a. Asynchrony in quantum-dot cellular automata nanocomputation: Elixir or Poison? IEEE Design Test of Computers 28, 5, 72--83. Google ScholarDigital Library
- Graziano, M., Vacca, M., Chiolerio, A., and Zamboni, M. 2011b. An NCL-HDL snake-clock-based magnetic qca architecture. IEEE Trans. Nanotech. 10, 5, 1141--1149. Google ScholarDigital Library
- He, C. and Jacome, M. 2006. RAS-NANO: A reliability-aware synthesis framework for reconfigurable nanofabrics. In Proceedings of the Design, Automation and Test in Europe (DATE'06). 1--6. Google ScholarDigital Library
- Huang, Y., Duan, X., Cui, Y., Lauhon, L. J., Kim, K.-H., and Lieber, C. M. 2001. Logic gates and computation from assembled nanowire building blocks. Science 294, 5545, 1313--1317.Google Scholar
- Hutchby, J., Cavin, R., Zhirnov, V., Brewer, J. E., and Bourianoff, G. 2008. Emerging nanoscale memory and logic devices: A critical assessment. Computer 41, 5, 28--32. Google ScholarDigital Library
- Lent, C. S., Tougaw, P., Porod, W., and Bernstein, G. 1993. Quantum cellular automata. Nanotechnology 4, 49--57.Google ScholarCross Ref
- Likharev, K. K. 2004. CMOL: A New Concept for Nanoelectronics. S. Pietroburgo, Russia.Google Scholar
- Likharev, K. K., Mayr, A., Muckra, I., and Türel, O. 2003. Crossnets: High-performance neuromorphic architectures for CMOL circuits. Ann. New York Acad. Sci. 1006, 146--156.Google ScholarCross Ref
- Lu, W. and Lieber, C. M. 2006. Semiconductor nanowires. J. Phys. D: Applied Physics, 39, 387--406.Google ScholarCross Ref
- Luo, Y., Collier, C. P., Jeppesen, J. O., Nielsen, K. A., Deionno, E., Ho, G., Perkins, J., Tseng, H.-R., Yamamoto, T., Stoddart, J. F., and Heath, J. R. 2002. Two-dimensional molecular electronics circuits. ChemPhysChem 3, 6, 519--525.Google ScholarCross Ref
- Martina, M. and Masera, G. 2010. Turbo NOC: A framework for the design of network-on-chip-based turbo decoder architectures. IEEE Trans. Circ. Syst. I, Regular Papers 57, 10, 1776--1789. Google ScholarDigital Library
- Moritz, C., Wang, T., Narayanan, P., Leuchtenburg, M., Guo, Y., Dezan, C., and Bennaser, M. 2007. Fault-tolerant nanoscale processors on semiconductor nanowire grids. IEEE Trans. Circuits and Systems I: Regular Papers, 54, 11, 2422--2437.Google ScholarCross Ref
- Moritz, C. A., and Wang, T. 2004. Latching on the wire and pipelining in nanoscale designs. In NSC-3. 1--7.Google Scholar
- Moritz, C. A. and Wang, T. 2006. Towards defect-tolerant nanoscale architectures. In Proceedings of the 6th IEEE Conference on Nanotechnology (IEEE-NANO 2006). 331--334.Google Scholar
- Motto, P., Dimonte, A., Rattalino, I., Demarchi, D., Piccinini, G., and Civera, P. 2012. Nanogap structures for molecular nanoelectronics. Nanoscale Res. Lett. 7, 113, 7.Google ScholarCross Ref
- Narayanan, P. and Moritz, C. A. 2009. Validating cascading of crossbar circuits with an integrated device-circuit exploration. In Proceeding of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOANCH'09). IEEE, 37--42. Google ScholarDigital Library
- Narayanan, P., Park, K. W., Chui, C. O., and Moritz, C. 2009. Manufacturing pathway and associated challenges for nanoscale computational systems. In Proceedings of 9th IEEE Conference on Nanotechnology (IEEE-NANO 2009). 119--122.Google Scholar
- Narayanan, P., Leuchtenburg, M., Wang, T., and Moritz, C. 2008a. CMOS control enabled single-type fet nasic. In Proceedings of the IEEE Symposium on VLSI (ISVLSI'08). 191--196. Google ScholarDigital Library
- Narayanan, P., Wang, T., Leuchtenburg, M., and Moritz, C. 2008b. Comparison of analog and digital nanosystems: Issues for the nano-architect. In Proceedings of the 2nd IEEE International Nanoelectronics Conference (INEC 2008). 1003--1008.Google Scholar
- Narayanan, P., Wang, T., Leuchtenburg, M., and Moritz, C. A. 2008c. Image processing architecture for semiconductor nanowire based fabrics. In Proceedings of the 8th IEEE Conference on Nanotechnology (NANO'08). 677--680.Google Scholar
- Pulimeno, A., Graziano, M., Abrardi, C., Demarchi, D., and Piccinini, G. 2011. Molecular QCA: A write-in system based on electric fields. In Proceeding of the 2011 IEEE 4th International Nanoelectronics Conference (INEC). 1--2.Google Scholar
- Pulimeno, A., Graziano, M., Demarchi, D., and Piccinini, G. 2012a. Towards a molecular QCA wire: Simulation of write-in and read-out systems. In Solid-State Electronics. Elsevier 1, 7.Google Scholar
- Pulimeno, A., Graziano, M., and Piccinini, G. 2012b. UDSM Trends Comparison: From technology roadmap to ultrasparc niagara2. IEEE Trans. Very Large Scale Integ (VLSI) Syst. 20, 7, 1341--1346. Google ScholarDigital Library
- Pulimeno, A., Graziano, M., Sanginario, A., Cauda, V., Demarchi, D., and Piccinini, G. 2013. Bis-ferrocene molecular QCA wire: ab-initio simulations of fabrication driven fault tolerance. IEEE Trans. Nanoelectron. 10.Google ScholarDigital Library
- Rueckes, T., Kim, K., Joselevich, E., Tseng, G. Y., Cheung, C. L., and Lieber, C. M. 2000. Carbon nanotube-based nonvolatile random access memory for molecular computing. Science 289, 5476, 94--97.Google Scholar
- Semiconductor Industry Association 2010. International Technology Roadmap of Semiconductors, 2010 Update. http://public.itrs.net.Google Scholar
- Vacca, M., Graziano, M., and Zamboni, M. 2012. Nanomagnetic logic microprocessor: Hierarchical power model. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 8, 8.Google Scholar
- Wang, K., Khitun, A., and Galatsis, K. 2007. More than moore's law: Nanofabrics and architectures. In Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM'07). IEEE. 139--143.Google Scholar
- Wang, T., Narayanan, P., and Andras, M. C. 2009. Heterogeneous two-level logic and its density and fault tolerance implications in nanoscale fabrics. IEEE Trans. Nanotechnology 8, 1, 22--30. Google ScholarDigital Library
- Wang, T., Narayanan, P., Leuchtenburg, M., and Moritz, C. 2008. (NASICs): A nanoscale fabric for nanoscale microprocessors. In Proceedings of the 2nd IEEE International Nanoelectronics Conference (INEC 2008). 989--994.Google Scholar
- Wang, Z. and Chakrabarty, K. 2007. Built-in self-test and defect tolerance in molecular electronics-based nanofabrics. J. Electron. Test. 23, 2--3, 145--161. Google ScholarDigital Library
- Zhang, S., Choi, M., and Park, N. 2004. Modeling yield of carbon-nanotube/silicon-nanowire FET-based nanoarray architecture with h-hot addressing scheme. In Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2004). 356--364. Google ScholarDigital Library
Index Terms
- Nanoarray architectures multilevel simulation
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