Santhosh Kumar Rethinagiri
Oscar Palomar
Rabie Ben Atitallah
ABSTRACT
Due to the ever increasing constraints on power consumption in embedded systems, this paper addresses the need for an efficient power modeling and estimation methodology based tool at system-level. On the one hand, today's embedded industries focus more on manufacturing RISC processor-based platforms as they are cost and power effective. On the other hand, modern embedded applications are becoming more and more sophisticated and resource demanding: multimedia (H.264 encoder and decoder), software defined radio, GPS, mobile applications, etc. The main objective of this paper focuses on the scarcity of a fast power modeling and an accurate power estimation tool at the system-level for complex embedded systems. In this paper, we propose a standalone simulation tool for power estimation at system-level. As a first step, we develop the power models at the functional level. This is done by characterizing the power behavior of RISC processor based platforms across a wide spectrum of application benchmark to understand their power profile. Then, we propose power models to cost-effectively estimate its power at run-time of complex embedded applications. The proposed power models rely on a few parameters which are based on functional blocks of the processor architecture. As a second step, we propose a power estimation simulator which is based on cycle-accurate full system simulation framework. The combination of the above two steps provides a standalone power estimation tool at the system-level.
The effectiveness of our proposed methodology is validated through an ARM9, an ARM Cortex-A8 and an ARM Cortex-A9 processor designed around the OMAP5912, OMAP 3530 and OMAP4430 boards respectively. The efficiency and the accuracy of our proposed tool is evaluated by using a variety of basic programs to complex benchmarks. Estimated power values are compared to real board measurements for the different processor architecture based platforms. Our obtained power estimation results provide less than 3% of error for ARM940T processor, 2.9% for ARM Cortex-A8 processor and 4.2% for ARM Cortex-A9 processor based platforms when compared to the other state-of-the-art power estimation tools.
- F. Bellosa. The benefits of event: driven energy accounting in power-sensitive systems. In Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system, EW 9, pages 37--42, New York, NY, USA, 2000. ACM. Google Scholar
Digital Library
- N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1--7, Aug. 2011. Google ScholarDigital Library
- D. Blouin and E. Senn. Cat: An extensible system-level power consumption analysis toolbox for model-driven design. In NEWCAS Conference (NEWCAS), 2010 8th IEEE International, pages 33--36, june 2010.Google ScholarCross Ref
- H. Blume, D. Becker, L. Rotenberg, M. Botteck, J. Brakensiek, and T. G. Noll. Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. J. Syst. Archit., 53(10):689--702, Oct. 2007. Google ScholarDigital Library
- A. Bogliolo, L. Benini, and G. D. Micheli. Regression-based rtl power modeling. ACM Transaction on Design Automation of Electronic Systems, 5:2000, 2000. Google ScholarDigital Library
- I. Böhm, B. Franke, and N. Topham. Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator. In Embedded Computer Systems (SAMOS), 2010 International Conference on, pages 1--10, july 2010.Google ScholarCross Ref
- C. Brandoleseč. A Codesign Approach to Software Power Estimation for Embedded Systems. PhD thesis, Politecnico di Milano, Institute of Electronics and Information, 2000.Google Scholar
- A. Butko, R. Garibotti, L. Ost, and G. Sassatelli. Accuracy evaluation of gem5 simulator system. In Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on, pages 1--7, july 2012.Google ScholarCross Ref
- C. X. Huang, B. Zhang, A.-C. Deng, and B. Swirski. The design and implementation of powermill. In M. Pedram, R. W. Brodersen, and K. Keutzer, editors, Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995, pages 105--110. ACM, 1995. Google ScholarDigital Library
- K. Jeong and A. B. Kahng. A power-constrained mpu roadmap for the international technology roadmap for semiconductors (itrs), 2010.Google Scholar
- J. Laurent, N. Julien, E. Senn, and E. Martin. Functional level power analysis: an efficient approach for modeling the power consumption of complex processors. In Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, volume 1, pages 666--667 Vol.1, feb. 2004. Google ScholarDigital Library
- S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 469--480, New York, NY, USA, 2009. ACM. Google ScholarDigital Library
- F. Najm. A survey of power estimation techniques in vlsi circuits. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2(4):446--455, dec. 1994. Google ScholarDigital Library
- Y. Patt, P. Foglia, E. Duesterwald, P. Faraboschi, and X. Martorell. High Performance Embedded Architectures and Compilers: HiPEAC 2010, Pisa, Italy. Lecture Notes in Computer Science/Theoretical Computer Science and General Issues. Springer, 2010. Google ScholarDigital Library
- N. Potlapally, A. Raghunathan, G. Lakshminarayana, M. Hsiao, and S. Chakradhar. Accurate power macro-modeling techniques for complex rtl circuits. In VLSI Design, 2001. Fourteenth International Conference on, pages 235--241, 2001. Google ScholarDigital Library
- S. Rethinagiri, R. Atitallah, and J. Dekeyser. A system level power consumption estimation for mpsoc. In System on Chip (SoC), 2011 International Symposium on, pages 56--61, 2011.Google ScholarCross Ref
- S. Rethinagiri, R. Ben Atitallah, S. Niar, E. Senn, and J. Dekeyser. Fast and accurate hybrid power estimation methodology for embedded systems. In Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on, pages 1--7, 2011.Google ScholarCross Ref
- S. K. Rethinagiri, R. Ben Atitallah, J.-L. Dekeyser, E. Senn, and S. Niar. An efficient power estimation methodology for complex risc processor-based platforms. In Proceedings of the Great Lakes Symposium on VLSI, GLSVLSI '12, pages 239--244, New York, NY, USA, 2012. ACM. Google ScholarDigital Library
- S. Thoziyoor and N. Muralimanohar. Cacti 5.0, 2007.Google Scholar
- V. Tiwari, S. Malik, A. Wolfe, and M. T.-C. Lee. Instruction level power analysis and optimization of software. In Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, VLSID '96, pages 326--, Washington, DC, USA, 1996. IEEE Computer Society. Google ScholarDigital Library
- R. Ubal, B. Jang, P. Mistry, D. Schaa, and D. Kaeli. Multi2sim: a simulation framework for cpu-gpu computing. In Proceedings of the 21st international conference on Parallel architectures and compilation techniques, PACT '12, pages 335--344, New York, NY, USA, 2012. ACM. Google ScholarDigital Library
- N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using simplepower. In Proceedings of the 27th annual international symposium on Computer architecture, ISCA '00, pages 95--106, New York, NY, USA, 2000. ACM. Google ScholarDigital Library
Index Terms
- System-level power estimation tool for embedded processor based platforms
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