The current trend towards multi/many-core computing architectures requires a global rethinking of software development and hardware design. The PARMA-DITAM workshop focuses on parallel programming models, design space exploration and tools, and run-time management techniques to exploit the features of multi/many-core computing architectures. It is centered on five main topics that cover: parallel programming models and languages, compilers and virtualization techniques; run-time adaptivity, run-time management, power management and memory management; heterogeneous and reconfigurable many-core architectures and design space exploration; design tools and methodologies for many-core architectures; and parallel applications for many-core platforms.
Proceeding Downloads
An Interactive Tool based on Polly for Detection and Parallelization of Loops
In many applications, such as signal and image processing, most computation time is spent within loops. Therefore, these loops are ideal candidates for performance increase when moving to parallel architectures, such as multi- or many-core systems. ...
On Expressing Strategies for Directive-Driven Multicore Programing Models
A common migration path for applications to high-performance multicore architectures relies on code annotations with concurrent semantics. Some annotations, however, are very target architecture specific and thus highly non-portable. In this paper we ...
Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
Heterogeneous Multi-Processor Systems-on-Chip (MPSoC) exhibit increased design complexity due to numerous architectural parameters and hardware/software partitioning schemes. Automated Design Space Exploration (DSE) becomes an essential design procedure ...
A cycle-accurate synthesizable MIPS simulator in Simulink
We introduce a novel methodology for creating a synthesizable, cycle-accurate simulator of the MIPS32 processor with concise, high-level programming expressions using Simulink and other matlab tools. The simulator, named SimuMIPS, is capable of running ...
Extending a Run-time Resource Management framework to support OpenCL and Heterogeneous Systems
From Mobile to High-Performance Computing (HPC) systems, performance and energy efficiency are becoming always more challenging requirements. In this regard, heterogeneous systems, made by a general-purpose processor and one or more hardware ...
Exploiting Performance Counters for Energy Efficient Co-Scheduling of Mixed Workloads on Multi-Core Platforms
Mainstream multicore architectures allow the execution of mixed workloads where multiple parallel applications run concurrently competing on shared computational resources. As different applications exhibit different and time varying resources needs, a ...
Fine-Grained Link Locking Within Power and Latency Transaction Level Modelling in Wormhole Switching Non-Preemptive Networks On Chip
An increasingly time-consuming part of the design flow of on-chip multiprocessors is simulation of the network on chip (NoC) architecture. Cycle-accurate simulation of state-of-the art network-on-chip interconnects can be prohibitively slow for ...
Recommendations
Vectorizing Unstructured Mesh Computations for Many-core Architectures
PMAM'14: Proceedings of Programming Models and Applications on Multicores and ManycoresAchieving optimal performance on the latest multi-core and many-core architectures depends more and more on making efficient use of the hardware's vector processing capabilities. While auto-vectorizing compilers do not require the use of vector ...
Vectorizing Unstructured Mesh Computations for Many-core Architectures
PMAM'14: Proceedings of Programming Models and Applications on Multicores and ManycoresAchieving optimal performance on the latest multi-core and many-core architectures depends more and more on making efficient use of the hardware's vector processing capabilities. While auto-vectorizing compilers do not require the use of vector ...
Vectorizing unstructured mesh computations for many-core architectures
Achieving optimal performance on the latest multi-core and many-core architectures increasingly depends on making efficient use of the hardware's vector units. This paper presents results on achieving high performance through vectorization on CPUs and ...
Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
PARMA-DITAM'2020 | 9 | 5 | 56% |
PARMA-DITAM '17 | 15 | 6 | 40% |
Overall | 24 | 11 | 46% |