skip to main content
research-article

Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs

Published:29 August 2014Publication History
Skip Abstract Section

Abstract

The efficiency and effectiveness of an adaptive router in an NoC-based multicore system is evaluated by the performance it achieves under varying inter-core communication traffic. A well-designed selection strategy plays an important role in an adaptive router to act upon dynamic traffic variations. The effectiveness of a selection strategy depends on what metric is used to represent congestion, how precisely this metric captures the actual congestion, and how much cost is involved in capturing the congestion on a real-time scale. Congestion is formed over a period of time due to cumulative and chain reaction effects. We propose novel history-based selection strategies that could be used with any adaptive, deadlock-free, minimal routing in mesh NoCs. Buffer occupancy time and rate of flit flow across reachable ports of neighboring routers in the recent past are captured, propagated, and maintained in a cost-effective way to compute the selection metric. Experimental results on real and synthetic workloads show that our proposed selection strategies significantly outperform state-of-the-art techniques.

References

  1. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, and Davide Patti. 2008. Implementation and analysis of a new selection strategy for adaptive routing in NoC. IEEE Trans. Comput. 57, 6, 809--820. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Sanaz Azampanah, Ahmad Khademzadeh, Nader Bagherzadeh, Majid Janidarmian, and Reza Shojaee. 2012. LATEX: New selection policy for adaptive routing in application-specific NoC. In Proceedings of the 20th Euromicro International Conference on Parallel Distributed and Network-Based Processing (PDP'12). 515--519. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Ge-Ming Chiu. 2000. The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11, 7, 729--738. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy, and Srinivas Devadas. 2009. Path-based, randomized, oblivious, minimal routing. In Proceedings of the 2nd International Workshop on Networks-on-Chip Architectures (NocArc'09). 23--28. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. William Dally. 1992. Virtual-channel flow control. IEEE Trans. Parallel Distrib. Syst. 3, 2, 194--205. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. William Dally and Brian Towles. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of the Design Automation Conference (DAC'01). 684--689. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. William Dally and Brian Towles. 2003. Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Fransisco. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Masoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, Juha Plosila, Pasi Liljeberg, Maurizio Palesi, and Hannu Tenhunen. 2012. HARAQ: Congestion-aware learning model for highly adaptive routing algorithm in on-chip networks. In Proceedings of the 6th International Symposium on Networks-on-Chip (NocS'12). 19--26. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, and Hannu Tenhunen. 2011. Agent-based on-chip network using efficient selection method. In Proceedings of the International Conference on VLSI and System-on-Chip (VLSI-SoC'11). 284--289.Google ScholarGoogle ScholarCross RefCross Ref
  10. Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, and Juha Plosila. 2011. Q-learning based congestion-aware routing algorithm for on-chip network. In Proceedings of the International Conference on Networked Embedded Systems for Enterprise Applications (NESEA'11). 1--7. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, and Pasi Liljeberg. 2012. Adaptive reinforcement learning method for networks-on-chip. In Proceedings of the International Conference on Embedded Computer Systems (SAMOS'12). 236--243.Google ScholarGoogle ScholarCross RefCross Ref
  12. Christopher J. Glass and Lionel M. Ni. 1992. The turn model for adaptive routing. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA'92). 278--287. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Paul Gratz, Boris Grot, and Stephen W. Keckler. 2008. Regional congestion awareness for load balance in networks-on-chip. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'08). 203--214.Google ScholarGoogle Scholar
  14. Amir Hosseini, Tamer Ragheb, and Yehia Massoud. 2008. A fault-aware dynamic routing algorithm for on-chip net-works. In Proceedings of the International Symposium on Circuits and Systems (ISCAS'08). 2653--2656.Google ScholarGoogle Scholar
  15. Jingcao Hu and Radu Marculescu. 2004. DyAD: Smart routing for networks-on-chip. In Proceedings of the Design Automation Conference (DAC'04). 260--264. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Nan Jiang, Daniel U. Becker, George Michelogiannakis, and William J. Dally. 2012. Network congestion avoidance through speculative reservation. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'12). 1--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. John Jose, K. V. Mahathi, J. Shiva Shankar, and Madhu Mutyam. 2012. TRACKER: A low overhead adaptive noc router with load balancing selection strategy. In Proceedings of the International Conference on Computer Aided Design (ICCAD'12). 564--568. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. John Jose, J. Shiva Shankar, K. V. Mahathi, Damarla Kranthi Kumar, and Madhu Mutyam. 2011. BOFAR: Buffer occupancy factor based adaptive router for mesh nocs. In Proceedings of the International Workshop on Networks-on-Chip Architectures (NocArc'11). 23--28. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Andrew B. Kahng, Li Bin, Li-Shiuan Peh, and Kambiz Samadi. 2009. Orion 2.0: A fast and accurate noc power and area model for early stage design space exploration. In Proceedings of the Design, Automation and Test in Europe Conference (DATE'09). 423--429. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Kevin Chang Kai-Wei, Rachata Ausavarungnirun, Chris Fallin, and Onur Mutlu. 2012. HAT: Heterogeneous adaptive throttling for on-chip networks. In Proceedings of the Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'12). 9--18. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. Abbas Eslami Kiasari, Axel Jantsch, and Zhonghai Lu. 2010. A framework for designing congestion-aware deterministic routing. In Proceedings of the International Workshop on Networks-on-Chip Architectures (NoCArc'10). 45--50. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Jongman Kim, Dongkook Park, Theocharis Theocharides, and Narayanan Vijaykrishnan. 2005. A low latency router supporting adaptivity for on-chip interconnects. In Proceedings of the Design Automation Conference (DAC'05). 559--1564. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Ying Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, and Sao Jie Chen. 2008. Fluidity concept for noc: A congestion avoidance and relief routing scheme. In Proceedings of the Annual IEEE International SoC Conference (SoCC'08). 65--70.Google ScholarGoogle Scholar
  24. Yanbin Lin and Dong Xiang. 2010. An effective congestion-aware selection function for adaptive routing in interconnection networks. In Proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'10). 156--165. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, and Zainalabedin Navabi. 2008. BARP-A dynamic routing protocol for balanced distribution of traffic in nocs. In Proceedings of the Design, Automation and Test in Europe Conference (DATE'08). 1408--1413. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. Pejman Lotfi-Kamran, Amir Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, and Zainalabedin Navabi. 2010. EDXY-A low cost congestion-aware routing algorithm for network-on-chips. J. Syst. Archit. 56, 7, 256--264. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Zhonghai Lu and Yi Wang. 2012. Dynamic flow regulation for ip integration on network-on-chip. In Proceedings of International Symposium on Networks-on-Chip (NoCS'12). 115--124. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. Ran Manevich, Israel Cidon, Avinoam Kolodny, and Isaskhar Walter. 2010. Centralized adaptive routing for nocs. IEEE Comput. Archit. Lett. 9, 2, 57--60. Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. Radu Marculescu, Umit Y. Ogras, Li Shiuan Peh, Natalie Enright Jerger, and Yatin Hoskote. 2009. Outstanding research problems in noc design: System, microarchitecture, and circuit perspectives. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 28, 1, 3--21. Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tsutomu Yoshinaga. 2009. Prediction router: Yet another low latency on-chip router architecture. In Proceedings of International Symposium on High Performance Computer Architecture (HPCA'09). 367--378.Google ScholarGoogle ScholarCross RefCross Ref
  31. Andres Mejia, Maurizio Palesi, Jos Flich, Shashi Kumar, Pedro Lopez, Rickard Holsmark, and Jos Duato. 2009. Region-based routing: A mechanism to support efficient routing algorithms in nocs. IEEE Trans. VLSI. Syst. 19, 2, 356--369. Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. Andres Mejia, Maurizio Palesi, Jos Flich, Shashi Kumar, Pedro Lopez, Rickard Holsmark, and Jos Duato. 2012. Efficient implementation of globally-aware network flow control. J. Parallel Distrib. Syst. 72, 1, 1412--1422. Google ScholarGoogle ScholarDigital LibraryDigital Library
  33. Behrad Niazmand, Midia Reshadi, and Akram Reza. 2012. PathAware: A contention-aware selection function for application-specific network-on-chips. In Proceedings of the NORCHIP International Conference (NORCHIP'12). 1--6.Google ScholarGoogle ScholarCross RefCross Ref
  34. Erland Nilsson, Mikael Millberg, Johnny Oberg, and Round Robin. 2003. Load distribution with the proximity congestion awareness in a network-on-chip. In Proceedings of the Design, Automation and Test in Europe Conference (DATE'03). 1126--1127. Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu, and Srinivasan Seshan. 2012. On-chip networks from a networking perspective: Congestion and scalability in many-core interconnects. In Proceedings of the ACM SIGCOMM Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication (SIGCOMM'12). 407--418. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Umit Y. Ogras and Radu Marculescu. 2006. Prediction based flow control for network-on-chip traffic. In Proceedings of the Design Automation Conference (DAC'06). 839--844. Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. Mukund Ramakrishna, Paul Gratz, and Alexander Sprintson. 2013. GCA: Global congestion awareness for load balance in networks-on-chip. In Proceedings of the International Symposium on Network on Chips (NOCS'13). 1--8.Google ScholarGoogle ScholarCross RefCross Ref
  38. Rohit Sunkam Ramanujam and Bill Lin. 2010. Destination-based adaptive routing on 2d mesh networks. In Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS'10). 19:1--19:12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  39. Diana Salemi, Maurizio Palesi, and Vincenzo Catania. 2011. Power-aware selection policy for networks on chip. In Proceedings on the 6th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS'11). 1--4.Google ScholarGoogle ScholarCross RefCross Ref
  40. Faizal Arya Samman, Thomas Hollstein, and Manfred Glesner. 2013. Runtime contention- and bandwidth-aware adaptive routing selection strategies for networks-on-chip. IEEE Trans. Parallel Distrib. Syst. 24, 7, 1411--1421. Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Loren Schwiebert and Renelius Bell. 2002. Performance tuning of adaptive wormhole routing through selection function choice. IEEE Trans. Parallel Distrib. Syst. 62, 7, 1121--1141. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. Ma Sheng, Natalie Enright Jerger, and Zhiying Wang. 2011. DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA'11). 413--424. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. Leonel Tedesco, Thiago Rosa, Fabien Clermidy, Ney Calazans, and Fernando Gehm Moraes. 2010. Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip. In Proceedings of the Symposium on Integrated Circuits and System Design (SBCCI'10). 91--96. Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. Rafael Ubal, Julio Sahuquillo, Salvador Petiti, and Pedro Lopez. 2007. Multi2Sim: A simulation framework to evaluate multicore-multithreaded processors. In Proceedings of the International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07). 62--68.Google ScholarGoogle ScholarCross RefCross Ref
  45. Chifeng Wang, Wen-Hsiang Hu, and Nader Bagherzadeh. 2013. Scalable load balancing congestion-aware network-on-chip router architecture. J. Comput. System Sci. 79, 4, 421--439. Google ScholarGoogle ScholarDigital LibraryDigital Library
  46. Wei Zhao and Yu Cao. 2007. Predictive technology model for nano-cmos design exploration. ACM J. Emerg. Technol. Comput. Syst. 3, 1, 1--17. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs

      Recommendations

      Comments

      Login options

      Check if you have access through your login credentials or your institution to get full access on this article.

      Sign in

      Full Access

      • Published in

        cover image ACM Transactions on Design Automation of Electronic Systems
        ACM Transactions on Design Automation of Electronic Systems  Volume 19, Issue 4
        August 2014
        246 pages
        ISSN:1084-4309
        EISSN:1557-7309
        DOI:10.1145/2663459
        • Editor:
        • Naehyuck Chang
        Issue’s Table of Contents

        Copyright © 2014 ACM

        © 2014 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        • Published: 29 August 2014
        • Accepted: 1 June 2014
        • Revised: 1 May 2014
        • Received: 1 January 2013
        Published in todaes Volume 19, Issue 4

        Permissions

        Request permissions about this article.

        Request Permissions

        Check for updates

        Qualifiers

        • research-article
        • Research
        • Refereed

      PDF Format

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader