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Energy Efficiency Analysis for the Single Frequency Approximation (SFA) Scheme

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Published:06 October 2014Publication History
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Abstract

Energy-efficient designs are important issues in computing systems. This article studies the energy efficiency of a simple and linear-time strategy, called the Single Frequency Approximation (SFA) scheme, for periodic real-time tasks on multicore systems with a shared supply voltage in a voltage island. The strategy executes all the cores at a single frequency to just meet the timing constraints. SFA has been adopted in the literature after task partitioning, but the worst-case performance of SFA in terms of energy consumption incurred is an open problem. We provide comprehensive analysis for SFA to derive the cycle utilization distribution for its worst-case behaviour for energy minimization. Our analysis shows that the energy consumption incurred by using SFA for task execution is at most 1.53 (1.74, 2.10, 2.69, respectively), compared to the energy consumption of the optimal voltage/frequency scaling, when the dynamic power consumption is a cubic function of the frequency and the voltage island has up to 4 (8, 16, 32, respectively) cores. The analysis shows that SFA is indeed an effective scheme under practical settings, even though it is not optimal. Furthermore, since all the cores run at a single frequency and no frequency alignment for Dynamic Voltage and Frequency Scaling (DVFS) between cores is needed, any unicore dynamic power management technique for reducing the energy consumption for idling can be easily incorporated individually on each core in the voltage island. This article also provides an analysis of energy consumption for SFA combined with procrastination for Dynamic Power Management (DPM), resulting in an increment of 1 from the previous results for task execution. Furthermore, we also extend our analysis for deriving the approximation factor of SFA for a multicore system with multiple voltage islands.

References

  1. Susanne Albers and Antonios Antoniadis. 2012. Race to idle: New algorithms for speed scaling with a sleep-state. In Proceedings of the 23rd ACM-SIAM Symposium on Discrete Algorithms (SODA'12). 1266--1285. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. Hakan Aydin and Qi Yang. 2003. Energy-aware partitioning for multiprocessor real-time systems. In Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS'03). 113--121. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Philippe Baptiste, Marek Chrobak, and Christoph Durr. 2012. Polynomial-time algorithms for minimum energy scheduling. ACM Trans. Algor. 8, 3. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Shekhar Borkar. 2007. Thousand core chips: A technology perspective. In Proceedings of the 44th Design Automation Conference (DAC'07). 746--749. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Jian-Jia Chen, Heng-Ruey Hsu, and Tei-Wei Kuo. 2006. Leakage-aware energy-efficient scheduling of real-time tasks in multiprocessor systems. In Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06). 408--417. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Jian-Jia Chen and Tei-Wei Kuo. 2007. Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'07). 289--294. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Jian-Jia Chen and Lothar Thiele. 2010. Energy-efficient scheduling on homogeneous multiprocessor platforms. In Proceedings of the ACM Symposium on Applied Computing (SAC'10). 542--549. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Pepijn J. de Langen and Ben H. H. Juurlink. 2006. Leakage-aware multiprocessor scheduling for low power. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS'06). Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Vinay Devadas and Hakan Aydin. 2010. Coordinated power management of periodic real-time tasks on chip multiprocessors. In Proceedings of the International Conference on Green Computing (GREENCOMP'10). 61--72. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Ronald L. Graham. 1969. Bounds on multiprocessing timing anomalies. SIAM J. Appl. Math. 17, 263--269.Google ScholarGoogle ScholarCross RefCross Ref
  11. Sebastian Herbert and Diana Marculescu. 2007. Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'07). 38--43. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, et al. 2011. A 48-core ia-32 processor in 45 nm cmos using on-die message-passing and dvfs for performance and power scaling. IEEE J. Solid-State Circ. 46, 1, 173--183.Google ScholarGoogle ScholarCross RefCross Ref
  13. Intel. 2009. Single-chip cloud computer (scc). http://www.intel.com/content/www/us/en/research/intel-labs-single-chip-cloud-overview-paper.html.Google ScholarGoogle Scholar
  14. Sandy Irani, Sandeep Shukla, and Rajesh Gupta. 2003. Algorithms for power savings. In Proceedings of the 14th Annual ACM-SIAM Symposium on Discrete Algorithms (SODA'03). 37--46. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. Ravindra Jejurikar, Cristiano Pereira, and Rajesh Gupta. 2004. Leakage aware dynamic voltage scaling for real-time embedded systems. In Proceedings of the 41st Design Automation Conference (DAC'04). 275--280. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. Chang L. Liu and James W. Layland. 1973. Scheduling algorithms for multiprogramming in a hard-real-time environment. J. ACM 20, 1, 46--61. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Gabriel A. Moreno and Dionisio de Niz. 2012. An optimal real-time voltage and frequency scaling for uniform multiprocessors. In Proceedings of the 18th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'12). 21--30. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Nikita Nikitin and Jordi Cortadella. 2012. Static task mapping for tiled chip multiprocessors with multiple voltage islands. In Proceedings of the 25th International Conference on Architecture of Computing Systems (ARCS'12). Springer, 50--62. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Santiago Pagani and Jian-Jia Chen. 2013. Energy efficient task partitioning based on the single frequency approximation scheme. In Proceedings of the 34th IEEE Real-Time Systems Symposium (RTSS'13). 308--318. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. Ronald L. Rardin. 1998. Optimization in Operations Research. Prentice Hall.Google ScholarGoogle Scholar
  21. Euiseong Seo, Jinkyu Jeong, Seon-Yeong Park, and Joonwon Lee. 2008. Energy efficient scheduling of real-time tasks on multicore processors. IEEE Trans. Parallel Distrib. Syst. 19, 11, 1540--1552. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Ruibin Xu, Dakai Zhu, Cosmin Rusu, Rami Melhem, and Daniel Mosse. 2005. Energy-efficient policies for embedded clusters. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05). 1--10. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Chuan-Yue Yang, Jian-Jia Chen, and Tei-Wei Kuo. 2005. An approximation algorithm for energy-efficient scheduling on a chip multiprocessor. In Proceedings of the Conference on Design, Automation, and Test in Europe (DATE'05). 468--473. Google ScholarGoogle ScholarDigital LibraryDigital Library

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          cover image ACM Transactions on Embedded Computing Systems
          ACM Transactions on Embedded Computing Systems  Volume 13, Issue 5s
          Special Issue on Risk and Trust in Embedded Critical Systems, Special Issue on Real-Time, Embedded and Cyber-Physical Systems, Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES)
          November 2014
          501 pages
          ISSN:1539-9087
          EISSN:1558-3465
          DOI:10.1145/2660459
          Issue’s Table of Contents

          Copyright © 2014 ACM

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          Publication History

          • Published: 6 October 2014
          • Accepted: 1 May 2014
          • Received: 1 September 2013
          Published in tecs Volume 13, Issue 5s

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