Marjan Asadinia
Mohammad Arjomand
Skip Abstract Section
Abstract
With current memory scalability challenges, Phase-Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that results in fast wear-out of memory cells. Worse, process variation in the deep-nanometer regime increases the variation in cell lifetime, resulting in an early and sudden reduction in main memory capacity due to the wear-out of a few cells. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer poor throughput or latency. In this article, we show that one of the inefficiency sources in current schemes, even when wear-leveling algorithms are used, is the nonuniform write endurance limit incurred by process variation, that is, when some memory pages have reached their endurance limit, other pages may be far from their limit. In this line, we present a technique that aims to displace a faulty page to a healthy page. This technique, called On-Demand Page Paired PCM (OD3P, for short), when applied at page level, can improve PCM time-to-failure by 20% on average for different multithreaded and multiprogrammed workloads while also improving IPC by 14% on average compared to previous page-level techniques. The comparison between line-level OD3P and previous line-level techniques reveals about 2× improvement of lifetime and performance.
- Mohammad Arjomand, Amin Jadidi, Ali Shafiee, and Hamid Sarbazi-Azad. 2011. A morphable phase change memory architecture considering frequent zero values. In Proceedings of the International Conference on Computer Design (ICCD'11). 373--380. Google Scholar
Digital Library
- Marjan Asadinia, Mohammad Arjomand, and Hamid Sarbazi-Azad. 2014. OD3P: On-demand page paired PCM. In Proceedings of the Annual Design Automation Conference (DAC'14). 1--6. Google ScholarDigital Library
- Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, and Viii Srinivasan. 2012. Efficient scrub mechanisms for error-prone emerging memories. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA'12). 1--12. Google ScholarDigital Library
- Rodolfo Azevedo, John D. Davis, Karin Strauss, Parikshit Gopalan, Mark Manasse, and Sergey Yekhanin. 2013. Zombie memory: Extending memory lifetime by reviving dead blocks. In Proceedings of the International Symposium on Computer Architecture (ISCA'13). 452--463. Google ScholarDigital Library
- Christian Bienia and Kai Li. 2009. PARSEC 2.0: A new benchmark suite for chip-multiprocessors. In Proceedings of the Annual Workshop on Modeling, Benchmarking and Simulation (MoBS'09).Google Scholar
- Jie Chen, Guru Venkataramani, and H. Howie Huang. 2012. RePRAM: Re-cycling PRAM faulty blocks for extended lifetime. In Proceedings of the International Conference on Dependable Systems and Networks (DSN'12). 1--12. Google ScholarDigital Library
- Sangyeun Cho and Hyunjin Lee. 2009. Flip-n-write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO'09). 347--357. Google ScholarDigital Library
- Jeremy Condit, Edmund B. Nightingale, Christopher Frost, Engin Ipek, Benjamin Lee, Doug Burger, and Derrick Coetzee. 2009. Better I/O through byte-addressable, persistent memory. In Proceedings of the ACM Symposium on Operating Systems Principles (SOSP'09). 133--146. Google ScholarDigital Library
- Xiangyu Dong and Yuan Xie. 2011. AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'11). 31--36. Google ScholarDigital Library
- Laura M. Grupp, John D. Davis, and Steven Swanson. 2013. The Harey Tortoise: Managing heterogeneous write performance in SSDs. In Proceedings of the USENIX Conference on Annual Technical Conference (ATC'13). 133--146. Google ScholarDigital Library
- Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, and Doug Burger. 2011. Preventing PCM banks from seizing too much power. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO'11). 186--195. Google ScholarDigital Library
- Morteza Hosseinzadeh, Mohammad Arjomand, and Hamid Sarbazi-Azad. 2014. Reducing access latency of MLC PCMs through line striping. In Proceedings of the International Symposium on Computer Architecture (ISCA'14). 277--288. Google ScholarDigital Library
- Stephen Hudgens and Brian Johnson. 2004. Overview of phase-change chalcogenide nonvolatile memory technology. MRS Bull. 29, 829--832.Google ScholarCross Ref
- Daniele Ielmini, Simone Lavizzari, Deepak Sharma, and Andrea L. Lacaita. 2007. Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation. In Proceedings of the International Electron Devices Meeting (IEDM'07). 939--942.Google Scholar
- Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger, and Thomas Moscibroda. 2010. Dynamically replicated memory: Building reliable systems from nanoscale resistive memories. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10). 3--14. Google ScholarDigital Library
- ITRS. 2011. Emerging research devices. http://www.itrs.net/.Google Scholar
- Majid Jalili, Mohammad Arjomand, and Hamid Sarbazi-Azad. 2014. A reliable 3D MLC PCM architecture with resistance drift predictor. In Proceedings of the International Conference on Dependable Systems and Networks (DSN'14). Google ScholarDigital Library
- Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers, and Jun Yang. 2011. LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory. In Proceedings of the International Conference on Dependable Systems and Networks (DSN'11). 221--232. Google ScholarDigital Library
- Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang, and Bruce R. Childers. 2012. Improving write operations in MLC phase change memory. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'12). 1--10. Google ScholarDigital Library
- Madhura Joshi, Wangyuan Zhang, and Tao Li. 2011. Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'11). 345--356. Google ScholarDigital Library
- Kim Kilbok. 2007. Main memory technology direction. In Proceedings of the Windows Hardware Engineering Conference (Win-Hec'07).Google Scholar
- Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the International Symposium on Computer Architecture (ISCA'09). 2--13. Google ScholarDigital Library
- Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav Hallberg, Johan Hogberg, Fredrik Larsson, Andreas Moestedt, and Bengt Werner. 2002. Simics: A full system simulation platform. Comput. 35, 2, 50--58. Google ScholarDigital Library
- Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. 2005. Multifacet's general execution-driven multi-processor simulator (GEMS) toolset. SIGARCH Comput. Archit. News 33, 4, 92--99. Google ScholarDigital Library
- Rino Micheloni, Alessia Marelli, and Rino Ravasio. 2008. Error Correction Codes for Non-Volatile Memories, 1st ed. Springer. Google ScholarDigital Library
- Moinuddin K. Qureshi. 2011. Pay-as-you-go: Low-overhead hard-error correction for phase change memories. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO'11). 318--328. Google ScholarDigital Library
- Moinuddin K. Qureshi, John Karidis, Michele M. Franceschini, Vijayalakshmi Srinivasan, Luis Lastras, and Bulent Abali. 2009a. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO'09). 14--23. Google ScholarDigital Library
- Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009b. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the International Symposium on Computer Architecture (ISCA'09). 24--33. Google ScholarDigital Library
- Moinuddin K. Qureshi, Michele M. Franceschini, Luis A. Lastras-Montano, and John P. Karidis. 2010a. Morphable memory system: A robust architecture for exploiting multi-level phase change memories. In Proceedings of the International Symposium on Computer Architecture (ISCA'10). 153--162. Google ScholarDigital Library
- Moinuddin K. Qureshi, Michele M. Franceschini, and Luis A. Lastras-Montano. 2010b. Improving read performance of phase change memories via write cancellation and write pausing. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'10). 1--11.Google Scholar
- Moinuddin K. Qureshi, Andre Seznec, Luis A. Lastras, and Michele M. Franceschini. 2011. Practical and secure PCM systems by online detection of malicious write streams. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA'11). 478--489. Google ScholarDigital Library
- Adrian Sampson, Jacob Nelson, Karin Strauss, and Luis Ceze. 2013. Approximate storage in solid-state memories. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO'13). 25--36. Google ScholarDigital Library
- Stuart Schechter, Gabriel H. Loh, Karin Straus, and Doug Burger. 2010. Use ECP, not ECC, for hard failures in resistive memories. In Proceedings of the International Symposium on Computer Architecture (ISCA'10). 141--152. Google ScholarDigital Library
- Nak Hee Seong, Dong Hyuk Woo, and Hsien-Hsin S. Lee. 2010a. Security refresh: Prevent malicious wearout and increase durability for phase-change memory with dynamically randomized address mapping. In Proceedings of the International Symposium on Computer Architecture (ISCA'10). 383--394. Google ScholarDigital Library
- Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, and Hsien-Hsin S. Lee. 2010b. SAFER: Stuck-at-fault error recovery for memories. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO'10). 115--124. Google ScholarDigital Library
- Nak Hee Seong, Sungkap Yeo, and Hsien-Hsin S. Lee. 2013. Tri-level-cell phase change memory: Toward an efficient and reliable memory system. In Proceedings of the International Symposium on Computer Architecture (ISCA'13). 440--451. Google ScholarDigital Library
- Cloyce D. Spradling. 2007. SPEC CPU2006 benchmark tools. SIGARCH Comput. Archit. News 35, 1, 130--134. Google ScholarDigital Library
- Wei Xu and Tong Zhang. 2010. Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory. In Proceedings of the International Symposium on Quality Electronic Design (ISQED'10). 356--361.Google Scholar
- Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, and Mattan Erez. 2011. FREE-p: Protecting non-volatile memory against both hard and soft errors. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA'11). 466--477. Google ScholarDigital Library
- Wangyuan Zhang and Tao Li. 2009. Characterizing and mitigating the impact of process variations on phase change based memory systems. In Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO'09). 2--13. Google ScholarDigital Library
- Wangyuan Zhang and Tao Li. 2011. Helmet: A resistance drift resilient architecture for multi-level cell phase change memory system. In Proceedings of the IEEE/IFIP International Conference on Dependable Systems Networks (DSN'11). 197--208. Google ScholarDigital Library
- Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. In Proceedings of the International Symposium on Computer Architecture (ISCA'09). 14--23. Google ScholarDigital Library
Index Terms
- Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing
Recommendations
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories
New phase-change memory (PCM) devices have low-access latencies (like DRAM) and high capacities (i.e., low cost per bit, like Flash). In addition to being able to scale to smaller cell sizes than DRAM, a PCM cell can also store multiple bits per cell (...
Increasing PCM main memory lifetime
DATE '10: Proceedings of the Conference on Design, Automation and Test in EuropeThe introduction of Phase-Change Memory (PCM) as a main memory technology has great potential to achieve a large energy reduction. PCM has desirable energy and scalability properties, but its use for main memory also poses challenges such as limited ...
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on MicroarchitecturePhase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure only a maximum of 107 - 108 writes, making a PCM based system have a lifetime ...
Comments