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Energy efficiency of a parallel HEVC software decoder for embedded devices

Published:06 May 2015Publication History

ABSTRACT

In the context of fast adoption and deployment of recent video compression standard and thanks to recent high performance embedded processors, software video decoding can be performed in real time. But, it becomes among the most energy-intensive applications. Current embedded processors are based on multi-core architecture with advanced convenient features such as Dynamic Voltage Frequency Scaling (DVFS) in order to reduce their power consumption, allowing low power video decoding when no hardware decoding support is available for a given device. This paper deals with energy efficiency impact of different parallelization strategies of a software High Efficiency Video Coding (HEVC) decoder on multi-core ARM big.LITTLE processor. These strategies include the exploitation of data and task-level parallelism, as well as the use of different available DVFS policies.

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              cover image ACM Conferences
              CF '15: Proceedings of the 12th ACM International Conference on Computing Frontiers
              May 2015
              413 pages
              ISBN:9781450333580
              DOI:10.1145/2742854

              Copyright © 2015 ACM

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              • Published: 6 May 2015

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