ABSTRACT
The clock networks of modern circuits must be able to operate in multiple corners and multiple modes (MCMM). Earlier studies on clock network synthesis for MCMM designs focus on the legalization of an initial clock network that has timing violations in different corners or modes. We propose a mode reconfigurable clock tree (MRCT) that is based on a correct-by-construction approach. An MRCT consists of multiple clock trees. Depending on the active mode, the MRCT is reconfigured such that one of the clock trees is activated to deliver the clock signal. To limit the overhead, the bottom part of the network (closer to the clock sinks) is shared among all of the clock trees, and only the top part of the network (closer to the clock source) is mode reconfigurable. The reconfiguration is realized using or-gates and a single one-input-multiple-output demultiplexer. The MRCT is constructed in a bottom-up fashion by iteratively merging subtrees to form larger subtrees. When two subtrees cannot be merged because of mode-incompatible constraints, an or-gate is inserted to separate the incompatible modes. Corner-incompatible constraints are resolved by reducing safety margins of appropriate skew constraints. The experimental results show that for a set of synthesized MCMM circuits with 715 to 13; 216 sequential elements, the proposed approach can achieve high yield.
- A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. ICCAD'03, pages 900--907, 2003. Google ScholarDigital Library
- T.-B. Chan, K. Han, A. B. Kahng, J.-G. Lee, and S. Nath. OCV-aware top-level clock tree optimization. GLSVLSI '14, pages 33--38, 2014. Google ScholarDigital Library
- W. Chan. Process corner estimation circuit with temperature compensation, 2009. US Patent 7,634,746.Google Scholar
- Y. P. Chen and D. F. Wong. An algorithm for zero-skew clock tree routing with buffer insertion. EDTC'96, pages 230--237, 1996. Google ScholarDigital Library
- R. Ewetz, S. Janarthanan, and C.-K. Koh. Fast clock skew scheduling based on sparse-graph algorithms. ASP-DAC '14, pages 472--477, 2014.Google Scholar
- J. Kim, D. Joo, and T. Kim. An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. DAC'13, pages 1--6, 2013. Google ScholarDigital Library
- J. Lu and B. Taskin. Post-CTS clock skew scheduling with limited delay buffering. In Cir. and Sys., pages 224--227, 2009.Google ScholarCross Ref
- NGSPICE. http://ngspice.sourceforge.net/.Google Scholar
- OpenCores. http://opencores.net/.Google Scholar
- A. Rajaram and D. Pan. Robust chip-level clock tree synthesis. CAD of Integrated Circuits and Sys., pages 877--890, 2011. Google ScholarDigital Library
- V. Ramachandran. Construction of minimal functional skew clock trees. ISPD'12, pages 119--120, 2012. Google ScholarDigital Library
- S. Roy, P. M. Mattheakis, L. Masse-Navette, and D. Z. Pan. Clock tree resynthesis for multi-corner multi-mode timing closure. ISPD'14, pages 69--76, 2014. Google ScholarDigital Library
- W. Shen, Y. Cai, W. Chen, Y. Lu, Q. Zhou, and J. Hu. Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED'10, pages 62--68, 2010.Google Scholar
- Y.-S. Su, W.-K. Hon, C.-C. Yang, S.-C. Chang, and Y.-J. Chang. Clock skew minimization in multi-voltage mode designs using adjustable delay buffers. CAD of ICs and Sys, pages 1921--1930, 2010. Google ScholarDigital Library
- C. Sze. ISPD 2010 high performance clock synthesis contest: Benchmark suite and results. ISPD'10, pages 143--143, 2010. Google ScholarDigital Library
- R. Ewetz S. Janarthanan, and C.-K. Koh. Benchmark circuits for clock scheduling and synthesis. https://purr.purdue.edu/publications/1759, 2015.Google Scholar
- C.-W. A. Tsao and C.-K. Koh. UST/DME: a clock tree router for general skew constraints. ACM TODAES, pages 359--379, 2002. Google ScholarDigital Library
- M. Zhao, K. Gala, V. Zolotov, Y. Fu, R. Panda, R. Ramkumar, and B. Agrawal. Worst case clock skew under power supply variations. TAU '02, pages 22--28, 2002. Google ScholarDigital Library
Index Terms
Construction of reconfigurable clock trees for MCMM designs
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