Andreas Tretter
ABSTRACT
Shared on-chip memory is common on state-of-the-art multicore platforms. In a number of designs, memory throughput is enhanced by providing multiple independent memory banks and spreading consecutive memory addresses to these (interleaving). This can reduce, but not eliminate, the number of access conflicts. In this paper, we statically analyse the probabilities and frequencies of these access conflicts and calculate the expected throughput for various hardware configurations and software applications. Using two techniques -- the classic occupancy distribution and a Markov model -- we are able to explain most of the underlying conflict mechanisms and to provide accurate estimations. We present the practical consequences for hardware and software design and establish an intuitive understanding of the characteristics of interleaved memory architectures.
- Adapteva. Epiphany Architecture Reference Manual. http://adapteva.com/docs/epiphany_arch_ref.pdf, 2008--2013.Google Scholar
- F. Baskett and A. J. Smith. Interference in Multiprocessor Computer Systems with Interleaved Memory. Comm. ACM, 19(6):327--334, June 1976. Google ScholarDigital Library
- L. Benini et al. P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator. In Proc. DATE, pages 983--987, 2012. Google ScholarDigital Library
- D. P. Bhandarkar. Analysis of memory interference in multiprocessors. Computers, IEEE Transactions on, 100(9):897--908, 1975. Google ScholarDigital Library
- D. P. Bhandarkar and S. H. Fuller. Markov Chain Models for Analyzing Memory Interference in Multiprocessor Computer Systems. In Proc. Symposium on Computer Architecture, ISCA '73, pages 1--6. ACM, 1973. Google ScholarDigital Library
- N. Binkert et al. The gem5 simulator. ACM SIGARCH Computer Architecture News, 39(2):1--7, 2011. Google ScholarDigital Library
- G. J. Burnett and E. G. Coffman, Jr. A Study of Interleaved Memory Systems. In Proc. Spring Joint Computer Conference, AFIPS '70 (Spring), pages 467--474. ACM, May 1970. Google ScholarDigital Library
- G. J. Burnett and E. G. Coffman, Jr. A Combinatorial Problem Related to Interleaved Memory Systems. J. ACM, 20:39--45, Jan. 1973. Google ScholarDigital Library
- W. Feller. An introduction to probability theory and its applications, volume 1. Wiley, 1968.Google Scholar
- M. R. Guthaus et al. MiBench: A free, commercially representative embedded benchmark suite. In Workload Characterization, 2001. WWC-4. 2001 IEEE Int'l Workshop on, pages 3--14. IEEE, 2001. Google ScholarDigital Library
- N. Johnson and S. Kotz. Urn models and their application: an approach to modern discrete probability theory. Wiley, 1977.Google Scholar
- R. v. Mises. Über Aufteilungs- und Besetzungswahrscheinlichkeiten. Revue de la Faculté de Sciences de l'Université d'Istanbul, pages 145--163, 1938--39.Google Scholar
- S. Rabinowitz. A model for interference in multiprocessors. Missouri Journal of Mathematical Sciences, 3:12--19, 1991.Google ScholarCross Ref
- B. R. Rau. Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System. IEEE Trans. Computers, 28(9):678--681, 1979. Google ScholarDigital Library
- B. R. Rau. Pseudo-randomly Interleaved Memory. In Proceedings of the 18th Annual International Symposium on Computer Architecture, ISCA '91, pages 74--83. ACM, 1991. Google ScholarDigital Library
- C. E. Skinner and J. R. Asher. Effects of storage contention on system performance. IBM Systems Journal, 8(4):319--333, 1969. Google ScholarDigital Library
- W. D. Strecker. An analysis of the instruction execution rate in certain computer structures. PhD thesis, 1970. Google ScholarDigital Library
Index Terms
- Interleaved multi-bank scratchpad memories: a probabilistic description of access conflicts
Recommendations
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
ARVLSI '97: Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a high performance microprocessor will typically send more accesses than ...
Scratchpad Memories for Parallel Applications in Multi-core Architectures
WSCAD-SSC '11: Proceedings of the 2011 Simpósio em Sistemas ComputacionaisScratchpad memories are largely used in embedded processorsdue to their reduced energy consumption and areacompared to traditional cache memories. In multi-core architectures, these memories are an interesting solution forthe storage of shared data and ...
Reducing Interference Among Vector Accesses in Interleaved Memories
Memory interference occurs when two or more concurrent data requests are addressed to the same main memory bank. In vector superconductors, this problem is serious due to the periodic interaction among vectors accesses, and can significantly reduce ...
Comments