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On wirelength estimations for row-based placement

Published:01 April 1998Publication History

ABSTRACT

Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop new wirelength estimation techniques appropriate for top-down floor-planning and placement synthesis of row-based VLSI layouts. Our methods include accurate, linear-time approaches, often with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). The new techniques offer advantages not only for early on-line wirelength estimation during top-down placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several theoretical contributions. Notably, we have resolved the long-standing discrepancy between region-based and bounding box-based RSMT estimation techniques; this leads to new estimates that are functions of instance size n and aspect ratio AR.

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                  cover image ACM Conferences
                  ISPD '98: Proceedings of the 1998 international symposium on Physical design
                  April 1998
                  220 pages
                  ISBN:158113021X
                  DOI:10.1145/274535

                  Copyright © 1998 ACM

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                  Publication History

                  • Published: 1 April 1998

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