Rakefet Kol
- 1.W.J. Bowhill, et. al., "Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU," Digital Technicaldournal, 7(1), pp. 100-115, 1995. Google Scholar
Digital Library
- 2.E. Brunvand, "The NSR Processor," Proc. of the 26th Annual Hawaii Int. Conf. on System Sciences, Vol. 1, pp. 428-435, 1993.Google Scholar
- 3.H.G. Cragon, Branch Strategy Taxonomy and Performance Models, IEEE Computer Society Press, 1992 Google ScholarDigital Library
- 4.I. David, R. Ginosar, and M. Yoeli, "Self-Timed Architecture of a Reducext Instruction Set Computer," in Asynchronous Design Methodologies, S. Furber and M. Edwards editors, IFIP Trans. Vol. A-28, Elsevier Science Publishers, pp. 29-43, 1993. Google ScholarDigital Library
- 5.M.E. Dean, STRiP: A Self-Timed RISC Processor, PhD thesis, Stanford Univ., 1992.Google Scholar
- 6.P.B. Endecott, SCALP: A Superscalar Asynchronous Low- Power Processor, PhD thesis, Dept. of Computer Science, Univ. of Manchester, 1995.Google Scholar
- 7.S.B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods, "A micropipelined ARM," V~I'93, 1993. Google ScholarDigital Library
- 8.D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, 8(3), pp. 231-274, 1987. Google ScholarDigital Library
- 9.J.L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann, 1996. Google ScholarDigital Library
- 10.M. Horten, "The Hot New Star of Microchips (Pentium Microprocessor)," New Scientist, 138(i 871), pp. 31-34, May 1993.Google Scholar
- 11.Intel Corporation, "Pentium Family User's Manual," 1994.Google Scholar
- 12.E. Jacobsen, E. Rotenberg, and J. E. Smith, "Assigning Confidence to Conditional Branch Prediction," Proc. of the 29th int Syrup. on Microarchitecture, pp. 142-152, Dec. 1996. Google ScholarDigital Library
- 13.R. Kol and R. Ginosar, "A Doubly-Latched Asynchronous Pipeline," ICCD'97.Google Scholar
- 14.R. Kol, R. Ginosar, and G. Samuel, "Statecharts Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems," IEICE Trans. on information and Systems, E80-D(3), pp. 308-314, Mar. 1997.Google Scholar
- 15.R. Kol, Sel~TimedAsynchronous Architecture of an Advanced General Purpose Microprocessor, Phi) thesis, Dept. of Electrical Engineering, Technion, Israel, 1997.Google Scholar
- 16.J.K.F. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design," IEEE Computer, 17(1), pp. 6-22, Jan. 1984.Google ScholarDigital Library
- 17.N. F. Magid, High Speed Computer Systems as a Result of Cuncurrent Execution of Sequential Instructions, PhD thesis, Dept. of Electrical Engineering, Illinois Institute of Technology, Chicago, illinois, 1980. Google ScholarDigital Library
- 18.N. Magid, G. Tjaden, and H. Messinger, "Exploitation of Concurrency by Virtual Elimination of Branch Instructions," Int. Conf. on Parallel Processing (ICPP), pp. 164-165, Aug. 1981.Google Scholar
- 19.A. Martin, et al., "The Design of an Asynchronous MIPS R3000 Microprocessor," Proc. Advanced Research in VLSI, Sept. 1997. Google ScholarDigital Library
- 20.A. J. Martin, et al., "The Design of an Asynchronous Microprocessor," Caitech-CS-TR-89-02, 1989. Google ScholarDigital Library
- 21.T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, and A. Takamura, "TITAC: Design of a Quasi-Delay-Insensitive Microprocessor," IEEE Design & Test of Computers, 11(2), pp. 50-63, Summer 1994. Google ScholarDigital Library
- 22.N. C. Paver, The Design and Implementation of an Asynchronous Microprocessor. PhD thesis, Dept. of Computer Science, Univ. of Manchester, 1994.Google Scholar
- 23.W.F. Richardson and E. Brunvand, "Fred: An Architecture for a Self-Timed Decoupled Computer," 2nd Int. Symp. on Advanced Research in Asynchronous Circuits and Systems, pp. 60-68, Mar. 1996. Google ScholarDigital Library
- 24.Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, 1997. http ://www. sematech, orgGoogle Scholar
- 25.H. Shaft, Avid Execution and Instruction Pruning in the Asynchronous Processor Kin, MSc thesis, Dept. of Electrical Engineering, Technion, Israel, 1998, in preparation.Google Scholar
- 26.J.E. Smith, "A Study of Branch Prediction Strategies," Proc. 8th Syrup. on Computer Architecture, pp. 135-148, May 1981. Google ScholarDigital Library
- 27.R. F. Sproull, I. E. Sutherland, and C. E. Molnar, "The Countertlow Pipeline Processor Architecture," IEEE Design & Test of Computers, 11(3), pp. 48-59, Fall 1994. Google ScholarDigital Library
- 28.D. Strassberg, "Cooling Hot Microprocessors," EDN (European Edition), 39(2), pp. 40-44,46,48, Jan. 1994.Google Scholar
- 29.A. K. Uht and V. Sindagi, "Disjoint Eager Execution: An Optimal Form of Speculative Execution," Proc. of the 28th Int. Syrup. on Microarchitecture, pp. 313-325, Nov. 1995. Google ScholarDigital Library
- 30.U. Weiser, "Future Directions in Microprocessor Design," Invited lecture, presented at 2nd Int. Syrup. on Advanced Research in Asynchronous Circuits and Systems, Mar. 1996.Google Scholar
- 31.T. L. Wolf, The A3000: An Asynchronous Version of the R3000, MSe thesis, Dept. of Computer Science, Univ. of Utah, 1992.Google Scholar
- 32.T.-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," The 19th Int. Symp. on Computer Architecture, pp. 124-134, May 1992. Google ScholarDigital Library
- 33.A. Yu, "The Future of Microprocessors," IEEE Micro, 16(6), pp. 46-53, Dec. 1996. Google ScholarDigital Library
Index Terms
- Kin: a high performance asynchronous processor architecture
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