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An extensible simulator for bus- and directory-based cache coherence

Published:13 June 2015Publication History

ABSTRACT

One of the most important concepts that must be understood by students of parallel computer architecture is cache coherence. Processors may change the value of shared variables by writing them in their private caches. These changes must be propagated to the far reaches of the system so that writes to each location are seen in the same sequence throughout the system. Of course, this can be achieved by various protocols, depending on the size of the system and the workload. Students can gain an in-depth understanding of these protocols by simulating them. Our approach is to provide students with an abstract simulator, which can be specialized through inheritance in C++ to model many different protocols. The protocols can be divided into bus based and directory based. Either of these can be invalidation or update. Hybrid and adaptive protocols can also be simulated. Among the protocols covered are MSI, MESI, MOESI, Firefly, Dragon, and a simplified SCI protocol. It would be easy to add additional protocols by subclassing appropriate classes.

References

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  4. Mohit Gambhir, Edward F. Gehringer, and Yan Solihin, "Animations of important concepts in parallel computer architecture," Workshop on Computer Architecture Education, International Symposium on Computer Architecture, San Diego, June 9, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Cache Coherence Simulator Student's VersionGoogle ScholarGoogle Scholar

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  • Published in

    cover image ACM Conferences
    WCAE '15: Proceedings of the Workshop on Computer Architecture Education
    June 2015
    64 pages
    ISBN:9781450337175
    DOI:10.1145/2795122

    Copyright © 2015 ACM

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    • Published: 13 June 2015

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    WCAE '15 Paper Acceptance Rate9of10submissions,90%Overall Acceptance Rate9of10submissions,90%

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