ABSTRACT
The design of tailored hardware has proven a successful strategy to reduce the timing analysis overhead for (hard) real-time systems. The stack cache is an example of such a design that has been proven to provide good average-case performance, while being easy to analyze.
So far, however, the analysis of the stack cache was limited to individual tasks, ignoring aspects related to multitasking. A major drawback of the original stack cache design is that, due to its simplicity, it cannot hold the data of multiple tasks at the same time. Consequently, the entire cache content needs to be saved and restored when a task is preempted.
We propose (a) an analysis exploiting the simplicity of the stack cache to bound the overhead induced by task preemption and (b) an extension of the design that allows to (partially) hide the overhead by virtualizing stack caches.
- S. Abbaspour, F. Brandner, and M. Schoeberl. A time-predictable stack cache. In Proc. of the Workshop on Software Technologies for Embedded and Ubiquitous Systems. 2013.Google ScholarCross Ref
- A. V. Aho, M. S. Lam, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, 2nd edition, 2006. Google ScholarDigital Library
- S. Altmeyer and C. Burguiere. A new notion of useful cache block to improve the bounds of cache-related preemption delay. In Euromicro Conf. on Real-Time Systems, 2009, ECRTS '09, pages 109--118. Google ScholarDigital Library
- S. Altmeyer, R. Davis, and C. Maiza. Improved cache related pre-emption delay aware response time analysis for fixed priority pre emptive systems. Real-Time Systems, 48(5):499--526, 2012. Google ScholarDigital Library
- D. Chabrol, D. Roux, V. David, M. Jan, M. A. Hmid, P. Oudin, and G. Zeppa. Time- and angle-triggered real-time kernel. In Design, Automation and Test in Europe, DATE'13, pages 1060--1062, 2013. Google ScholarDigital Library
- M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. In Proc. of the Workshop on Workload Characterization, WWC '01, 2001. Google ScholarDigital Library
- M. Jan, V. David, J. Lalande, and M. Pitel. Usage of the safety-oriented real-time oasis approach to build deterministic protection relays. In Symp. on Industrial Embedded Systems, SIES'10, pages 128--135, 2010.Google ScholarCross Ref
- A. Jordan, F. Brandner, and M. Schoeberl. Static analysis of worst-case stack cache behavior. In Proc. of the Conf. on Real-Time Networks and Systems, RTNS'13, pages 55--64, 2013. Google ScholarDigital Library
- C.-G. Lee, J. Hahn, Y.-M. Seo, S. L. Min, R. Ha, S. Hong, C. Y. Park, M. Lee, and C. S. Kim. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans. Comput., 47(6):700--713, 1998. Google ScholarDigital Library
- S. Metzlaff, I. Guliashvili, S. Uhrig, and T. Ungerer. A dynamic instruction scratchpad memory for embedded processors managed by hardware. In Proc. of the Architecture of Computing Systems Conf., pages 122--134. Springer, 2011. Google ScholarDigital Library
- J. Mische, S. Uhrig, F. Kluge, and T. Ungerer. Using smt to hide context switch times of large real-time tasksets. In Proc. of Conf. on Embedded and Real-Time Computing Systems and Applications, RTCSA'10, pages 255--264, 2010. Google ScholarDigital Library
- L. E. Olson, Y. Eckert, S. Manne, and M. D. Hill. Revisiting stack caches for energy efficiency. Technical Report TR1813, University of Wisconsin, 2014.Google Scholar
- J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee. PRET DRAM controller: Bank privatization for predictability and temporal isolation. In Proc. of the Conf. on Hardware/Software Codesign and System Synthesis, pages 99--108, 2011. Google ScholarDigital Library
- C. Rochange, S. Uhrig, and P. Sainrat. Time-Predictable Architectures. ISTE Wiley, 2014. Google ScholarDigital Library
- S. Abbaspour and F. Brandner. Alignment of memory transfers of a time-predictable stack cache. In Proc. of the Junior Researcher Workshop on Real-Time Computing. 2014.Google Scholar
- S. Abbaspour, A. Jordan, and F. Brandner. Lazy spilling for a time-predictable stack cache: Implementation and analysis. In Proc. of the Workshop on Worst-Case Execution Time Analysis, volume 39 of OASICS, pages 83--92, 2014.Google Scholar
- M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner, C. Probst, S. Karlsson, and T. Thorn. Towards a time-predictable dual-issue microprocessor: The patmos approach. In Proc. of Bringing Theory to Practice: Predictability and Performance in Embedded Systems, volume 18, pages 11--21. OASICS, 2011.Google Scholar
- V. Soundararajan and A. Agarwal. Dribbling registers: A mechanism for reducing context switch latency in large-scale multiprocessors. Technical report, 1992.Google Scholar
- E. Tune, R. Kumar, D. M. Tullsen, and B. Calder. Balanced multithreading: Increasing throughput via a low cost multithreading hierarchy. In Proc. of the Symp. on Microarchitecture, MICRO'04, pages 183--194, 2004. Google ScholarDigital Library
- R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. Trans. Comp.-Aided Des. Integ. Cir. Sys., 28(7):966--978, 2009. Google ScholarDigital Library
Index Terms
- Efficient context switching for the stack cache: implementation and analysis
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