Abstract
Improving the endurance of phase change memory (PCM) is a fundamental issue when PCM technology is considered as an alternative to main memory usage. Existing wear-leveling techniques overcome this challenge through constantly remapping hot virtual pages, thus engendering a fair amount of extra write operations to PCM and imposing considerable performance and energy overhead. Our observation is that it is unnecessary to fully balance the accesses to different physical page frames during the execution of each process. Instead, since endurance is a lifetime factor, the hot virtual pages of different processes can be mapped to different physical pages in the PCM. Leveraging this property, we develop a wear-resistant page allocation algorithm, which exploits the diverse write characteristics of different program segments to improve PCM write endurance within almost no extra remapping cost in terms of energy and performance. The results of experiments conducted based on SPEC benchmarks show that the proposed technique can prolong PCM lifetime by hundreds of times within nearly zero searching and remapping overhead.
- C. H. Chen, P. C. Hsiu, T. W. Kuo, C. L. Yang, and C. Y. M. Wang. 2012. Age-based PCM wear leveling with nearly zero search cost. In Proceedings of the Design Automation Conference (DAC’12). 453--458. Google ScholarDigital Library
- S. Y. Cho and H. J. Lee. 2009. Flip-n-write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the International Symposium on Microarchitecture (MICRO’09). 347--357. Google ScholarDigital Library
- J. Fan, S. Jiang, J. Shu, Y. Zhang, and W. Zhen. 2013. Aegis: Partitioning data block for efficient recovery of stuck-at-faults in phase change memory. In Proceedings of the International Symposium on Microarchitecture (MICRO’13). 433--444. Google ScholarDigital Library
- A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Mosse. 2010. Increasing PCM main memory lifetime. In Proceedings of the Design, Automation, and Test in Europe Conference and Exhibition (DATE’10). 914--919. Google ScholarDigital Library
- J. T. Hu, C. J. Xue, W. C. Tseng, Y. He, M. K. Qiu, and E. H. M. Sha. 2010. Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. In Proceedings of the Design Automation Conference (DAC’10). 350--355. Google ScholarDigital Library
- ITRS. 2013. International Technology Roadmap for Semiconductors (ITRS). Retrieved March 28, 2016, from http://www.itrs2.net/2013-itrs.html.Google Scholar
- L. Jiang, Y. Du, Y. T. Zhang, B. R. Childers, and J. Yang. 2011. LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory. In Proceedings of the International Conference on Dependable Systems and Networks (DSN’11). 221--232. Google ScholarDigital Library
- H. Aghaei Khouzani, Y. Xue, C. Yang, and A. Pandurangi. 2014. Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’14). Google ScholarDigital Library
- H. Aghaei Khouzani, C. Yang, and J. Hu. 2015. Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategy. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’15). 508--513.Google Scholar
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. 2009. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the International Symposium on Computer Architecture (ISCA’09). 2--13. Google ScholarDigital Library
- H. G. Lee, S. C. Baek, C. Nicopoulos, and J. M. Kim. 2011a. An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems. In Proceedings of the International Conference on Computer Design (ICCD’11). 381--387. Google ScholarDigital Library
- S. Y. Lee, H. K. Bahn, and S. H. Noh. 2011b. Characterizing memory write references for efficient management of hybrid PCM and DRAM memory. In Proceedings of the International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS’11). 168--175. Google ScholarDigital Library
- D. Liu, T. Z. Wang, Y. Wang, Z. L. Shao, Q. F. Zhuge, and E. Sha. 2013. Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’13). 22--25.Google Scholar
- R. Melhem, R. Maddah, and C. Sangyeun. 2012. RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory. In Proceedings of the International Conference on Dependable Systems and Networks (DSN’12). 1--12. Google ScholarDigital Library
- Y. H. Park, D. J. Shin, S. K. Park, and K. H. Park. 2011. Power-aware memory management for hybrid main memory. In Proceedings of the International Conference on Next Generation Information Technology (ICNIT’11). 82--85.Google Scholar
- Pin. 2012. PIN—A Dynamic Binary Instrumentation Tool. Retrieved March 28, 2016, from http://software. intel.com/en-us/articles/pintool.Google Scholar
- A. Poorghanad, A. Sadr, and A. Kashanipour. 2008. Generating high quality pseudo random number using evolutionary methods. In Proceedings of the International Conference on Computational Intelligence and Security (CIS’08). 331--335. Google ScholarDigital Library
- M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali. 2009a. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In Proceedings of the International Symposium on Microarchitecture (MICRO’09). 14--23. Google ScholarDigital Library
- M. K. Qureshi, V. Srinivasan, and J. A. Rivers. 2009b. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the International Symposium on Computer Architecture (ISCA’09). 24--33. Google ScholarDigital Library
- S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y. C. Chen, and R. M. Shelby. 2008. Phase-change random access memory: A scalable technology. IBM Journal of Research and Development 52, 4.5, 465--479. Google ScholarDigital Library
- N. H. Seong, D. H. Woo, and H. H. S. Lee. 2010a. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In Proceedings of the International Symposium on Computer Architecture (ISCA’10). 383--394. Google ScholarDigital Library
- N. H. Seong, D. H. Woo, V. Srinivasan, J. A. Rivers, and H. H. S. Lee. 2010b. SAFER: Stuck-at-fault error recovery for memories. In Proceedings of the International Symposium on Microarchitecture (MICRO’10). 115--124. Google ScholarDigital Library
- A. S. Tanenbaum. 2001. Modern Operating Systems (2nd ed.). Prentice Hall. Google ScholarDigital Library
- W. Zhang and T. Li. 2009. Characterizing and mitigating the impact of process variations on phase change based memory systems. In Proceedings of the International Symposium on Microarchitecture (MICRO’09). 2--13. Google ScholarDigital Library
- M. Zhao, L. Jiang, Y. Zhang, and C. J. Xue. 2014a. SLC-enabled wear leveling for MLC PCM considering process variation. In Proceedings of the Design Automation Conference (DAC’14). 1--6. Google ScholarDigital Library
- M. Zhao, L. Shi, C. Yang, and C. J. Xue. 2014b. Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM based main memory. In Proceedings of the International Conference on Computer Design (ICCD’14). 16--21.Google Scholar
- M. Zhou, Y. Du, B. Childers, R. Melhem, and D. Moose. 2012. Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems. ACM Transactions on Architecture and Code Optimization 8, 4, Article No. 53. Google ScholarDigital Library
- P. Zhou, B. Zhao, J. Yang, and Y. T. Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. In Proceedings of the International Symposium on Computer Architecture (ISCA’09). 14--23. Google ScholarDigital Library
Index Terms
- Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation
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