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Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Published:12 May 2016Publication History
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Abstract

With dramatic growth of data and rapid enhancement of computing powers, data accesses become the bottleneck restricting overall performance of a computer system. Emerging phase-change memory (PCM) is byte-addressable like DRAM, persistent like hard disks and Flash SSD, and about four orders of magnitude faster than hard disks or Flash SSDs for typical file system I/Os. The maturity of PCM from research to production provides a new opportunity for improving the I/O performance of a system. However, PCM also has some weaknesses, for example, long write latency, limited write endurance, and high active energy. Existing processor cache systems, main memory systems, and online storage systems are unable to leverage the advantages of PCM, and/or to mitigate PCM’s drawbacks. The reason behind this incompetence is that they are designed and optimized for SRAM, DRAM memory, and hard drives, respectively, instead of PCM memory. There have been some efforts concentrating on rethinking computer architectures and software systems for PCM. This article presents a detailed survey and review of the areas of computer architecture and software systems that are oriented to PCM devices. First, we identify key technical challenges that need to be addressed before this memory technology can be leveraged, in the form of processor cache, main memory, and online storage, to build high-performance computer systems. Second, we examine various designs of computer architectures and software systems that are PCM aware. Finally, we obtain several helpful observations and propose a few suggestions on how to leverage PCM to optimize the performance of a computer system.

References

  1. W. Arden. 2009. Semiconductor Industries Association - International Technology Roadmap for Semiconductors. http://www.itrs2.net/itrs-reports.html.Google ScholarGoogle Scholar
  2. R. Azevedoy, J. D. Davisz, and K. Straussz. 2013. Zombie memory: Extending memory lifetime by reviving dead blocks. In The 40th Annual International Symposium on Computer Architecture. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. S. Baek, J. Choi, D. Lee, and S. H. Noh. 2013. Energy-efficient and high-performance software architecture for storage class memory. ACM Transactions on Embedding Computing Systems 12, 3, Article 81, 22 pages. DOI:http://dx.doi.org/10.1145/2442116.2442131 Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. S. Baek, H. G. Lee, C. Nicopoulos, and J. Kim. 2012. A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures. In Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI’12). ACM, New York, NY, 345--350. DOI:http://dx.doi.org/10.1145/2206781.2206865 Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. R. Biswas and E. Ort. 2006. The java persistence API - a simpler programming model for entity persistence.Retrieved March 30, 2016 from http://java.sun.com/developer/technicalArticles/J2EE/jpa/.Google ScholarGoogle Scholar
  6. S. Bock, B. Childers, R. Melhem, D. Mossé, and Y. Zhang. 2011. Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’11). IEEE, 56--65. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson B. et al. 2010. Phase change memory technology. Journal of Vacuum Science and Technology B 28, 223--262.Google ScholarGoogle ScholarCross RefCross Ref
  8. G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy. 2008. Overview of candidate device technologies for storage-class memory. IBM Journal of Research and Development 52, 4.5, 449--464. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. J. Chen, R. C. Chiang, H. H. Huang, and G. Venkataramani. 2011a. Energy-aware writes to non-volatile main memory. ACM SIGOPS Operating Systems Review 45, 3, 48--52. DOI:http://dx.doi.org/10.1145/2094091.2094104 ACM New York, NY, USA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. S. Chen, P. B. Gibbons, and S. Nath. 2011b. Rethinking database algorithms for phase change memory. In CIDR.Google ScholarGoogle Scholar
  11. S. Cho and H. Lee. 2009. Flip-n-write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’09). ACM, New York, NY, 347--357. DOI:http://dx.doi.org/10.1145/1669112.1669157 Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson. 2011. NV-heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’11). Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee. 2009. Better I/O through byte-addressable, persistent memory. In Proceedings of the ACM SIGOPS 22nd Symposium on Operating Systems Principles (SOSP’09). New York, NY, 133--146. DOI:http://dx.doi.org/10.1145/1629575.1629589 Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. G. Dhiman, R. Ayoub, and T. Rosing. 2009. PDRAM: A hybrid PRAM and DRAM main memory system. In Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC’09). 664--669. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. J. Dong, L. Zhang, Y. Han, and Y. Wang. 2011b. Wear rate leveling: Lifetime enhancement of PRAM with endurance variation. In Proceedings of the 51st Annual Design Automation Conference (DAC’11). ACM, New York, NY, Article 36, 6 pages. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. X. Dong, N. P. Jouppi, and Y. Xie. 2009a. PCRAMsim: System-level performance energy and area modeling for phase-change RAM. In IEEE/ACM International Conference on Computer-Aided Design. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. X. Dong, N. Muralimanohar, N. Jouppi, R. Kaufmann, and Y. Xie. 2009b. Leveraging 3d PCRAM technologies to reduce checkpoint overhead for future exascale systems. In Super Computing Conference (SC’09). Portland, OR. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. 2008. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In Proceedings of the 45th Annual Design Automation Conference. Anaheim, CA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. X. Dong, Y. Xie, N. Muralimanohar, and N. P. Jouppi. 2011a. Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Transactions on Architecture and Code Optimization 8, 6, 1--29. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. K. Doshi and P. Varman. 2012. WrAP: Managing byte-addressable persistent memory. In Memory Architecture and Organization Workshop (MEAOW’12).Google ScholarGoogle Scholar
  21. U. Drepper. 2007. What Every Programmer Should Know About Memory. Retrieved March 30, 2016 from http://people.redhat.com/drepper/cpumemory.pdf.Google ScholarGoogle Scholar
  22. Y. Du, M. Zhou, B. R. Childers, R. Melhem, and D. Mosse. 2013. Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory. ACM Transactions on Architecture and Code Optimization 9, 4. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson. 2014a. System software for persistent memory. In Proceedings of the 9th European Conference on Computer Systems (EuroSys’14). ACM, New York, NY, Article 15, 15 pages. DOI:http://dx.doi.org/10.1145/2592798.2592814 Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson. 2014b. System software for persistent memory. In Proceedings of the 9th European Conference on Computer Systems (EuroSys’14). ACM, New York, NY, Article 15, 15 pages. DOI:http://dx.doi.org/10.1145/2592798.2592814 Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. J. Fan, S. Jiang, J. Shu, L. Sun, and Q. Hu. 2014. WL-reviver: A framework for reviving any wear-leveling techniques in the face of failures on phase change memory. In Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. J. Fan, S. Jiang, J. Shu, H. Zhang, and W. Zhen. 2013. Aegis: Partitioning data block for efficient recovery of stuck-at-faults in phase change memory. In 46th Annual IEEE/ACM International Symposium on Microarchitecture. Google ScholarGoogle ScholarDigital LibraryDigital Library
  27. Y. Fang, H. Li, and X. Li. 2012. SoftPCM: Enhancing energy efficiency and lifetime of phase change memory in video applications via approximate write. In 2012 IEEE 21st Asian Test Symposium (ATS). IEEE, 131--136. Google ScholarGoogle ScholarDigital LibraryDigital Library
  28. S. Gao, J. Xu, B. He, B. Choi, and H. Hu. 2011. PCMLogging: Reducing transaction logging overhead with PCM. In Proceedings of the 20th ACM International Conference on Information and Knowledge Management (CIKM’11). Google ScholarGoogle ScholarDigital LibraryDigital Library
  29. S. Guo, Z. Liu, D. Wang, H. Wang, and G. Li. 2012. Wear-resistant hybrid cache architecture with phase change memory. In Proceedings of the 2012 IEEE 7th International Conference on Networking, Architecture, and Storage (NAS’12). IEEE Computer Society, Washington, DC, 268--272. DOI:http://dx.doi.org/10.1109/NAS.2012.37 Google ScholarGoogle ScholarDigital LibraryDigital Library
  30. J. Hu, Q. Zhuge, C. J. Xue, W. Tseng, and E. H.-M. Sha. 2013. Software enabled wear-leveling for hybrid PCM main memory on embedded systems. In 13th ACM/IEEE Design, Automation and Test in Europe. Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. A. N. Jacobvitz, R. Calderbank, and D. J. Sorin. 2013. Coset coding to extend the lifetime of memory. In Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA’13). IEEE Computer Society, Washington, DC, 222--233. DOI:http://dx.doi.org/10.1109/HPCA.2013.6522321 Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. ITRS. 2007. Process Integration, Devices and Structures, International Technology Roadmap for Semiconductors. http://www.itrs2.net/itrs-reports.html.Google ScholarGoogle Scholar
  33. L. Jiang, Y. Du, B. Zhao, Y. Zhang, B. R. Childers, and J. Yang. 2013. Hardware-assisted cooperative integration of wear-leveling and salvaging for phase change memory. ACM Transactions on Architecture and Code Optimization 10, 2. Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. L. Jiang, Y. Zhang, and J. Yang. 2012. ER: Elastic reset for low power and long endurance MLC based phase change memory. In Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’12). ACM, New York, NY, 39--44. DOI:http://dx.doi.org/10.1145/2333660.2333672 Google ScholarGoogle ScholarDigital LibraryDigital Library
  35. Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, and Y. Xie. 2010. Energy- and endurance-aware design of phase change memory caches. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE’10). European Design and Automation Association, Leuven, Belgium, 136--141. http://dl.acm.org/citation.cfm?id=1870926.1870961. Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. J.-Y. Jung and S. Cho. 2013. Memorage: Emerging persistent RAM based malleable main memory and storage architecture. In Proceedings of the 27th International ACM Conference on International Conference on Supercomputing (ICS’13). ACM, New York, NY, 115--126. DOI:http://dx.doi.org/10.1145/2464996.2465005 Google ScholarGoogle ScholarDigital LibraryDigital Library
  37. S. Kannan, A. Gavrilovska, and K. Schwan. 2014. Reducing the cost of persistence for nonvolatile heaps in end user devices. In IEEE 20th International Symposium on High Performance Computer Architecture (HPCA’14). IEEE, 512--523.Google ScholarGoogle Scholar
  38. D. Kau, S. Tang, I. V. Karpov, and R. Dodge. 2009. A stackable cross point phase change memory. In Electron Devices Meeting (IEDM’09). 1--4. DOI:http://dx.doi.org/10.1109/IEDM.2009.5424263Google ScholarGoogle Scholar
  39. H. Kim, S. Seshadri, C. L. Dickey, and L. Chiu. 2014. Evaluating phase change memory for enterprise storage systems: A study of caching and tiering approaches. In Proceedings of the 12th USENIX Conference on File and Storage Technologies (FAST’14). USENIX Association, Berkeley, CA, 33--45. http://dl.acm.org/citation.cfm?id=2591305.2591309. Google ScholarGoogle ScholarDigital LibraryDigital Library
  40. M. H. Kryder and C. S. Kim. 2009. After hard drives - what comes next? IEEE Transactions on Magnetics 45, 3406--3413.Google ScholarGoogle ScholarCross RefCross Ref
  41. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. 2009. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the 36th International Symposium on Computer Architecture (ISCA’09). Austin, TX, 2--13. Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger. 2010. Phase-change technology and the future of main memory. IEEE Micro 30, 1, 131--141. Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger. 2013. On-demand snapshot: An efficient versioning file system for phase-change memory. IEEE Transactions on Knowledge and Data Engineering 25, 12, 2841--2853. Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. E. Lee, H. Bahn, and S. H. Noh. 2013. Unioning of the buffer cache and journaling layers with non-volatile memory. In Proceedings of the 11th USENIX Conference on File and Storage Technologies (FAST’13). USENIX Association, Berkeley, CA, 73--80. http://dl.acm.org/citation.cfm?id=2591272.2591280. Google ScholarGoogle ScholarDigital LibraryDigital Library
  45. C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. W. Keller. 2003. Energy management for commercial servers. Computer 36, 12, 39--48. Google ScholarGoogle ScholarDigital LibraryDigital Library
  46. D. L. Lewis and H.-H. S. Lee. 2009. Architectural evaluation of 3D stacked RRAM caches. In IEEE International 3D System Integration Conference.Google ScholarGoogle Scholar
  47. D. Li, J. Vetter, G. Marin, C. McCurdy, C. Cira, Z. Liu, and W. Yu. 2012. Identifying opportunities for byte-addressable non-volatile memory in extreme-scale scientific applications. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS’12). Google ScholarGoogle ScholarDigital LibraryDigital Library
  48. J.-T. Lin, Y.-B. Liao, M.-H. Chiang, I.-H. Chiu, C.-L. Lin, W.-C. Hsu, P.-C. Chiang, S.-S. Sheu, W.-H. Hsu, Y.-Y. Liu, K.-L. Su, M.-J. Kao, and M.-J. Tsai. 2009. Design optimization in write speed of multi-level cell application for phase change memory. In Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC’09). IEEE, Article 5394196, 4 pages. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5394196.Google ScholarGoogle Scholar
  49. D. Liu, T. Wang, Y. Wang, Z. Shao, Q. Zhuge, and E. Sha. 2013. Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems. In Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13).Google ScholarGoogle Scholar
  50. R.-S. Liu, D.-Y. Shen, C.-L. Yang, S.-C. Yu, and C.-Y. M. Wang. 2014. NVM duet: Unified working memory and persistent store architecture. In Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’14). ACM, New York, NY, 455--470. DOI:http://dx.doi.org/10.1145/2541940.2541957 Google ScholarGoogle ScholarDigital LibraryDigital Library
  51. L. Long, D. Liu, J. Hu, S. Gu, Q. G. Zhuge, and E. H.-M. Sha. 2014. A space allocation and reuse strategy for PCM-based embedded systems. Journal of Systems Architecture 60, 8, 655--667. DOI:http://dx.doi.org/10.1016/j.sysarc.2014.07.002 Google ScholarGoogle ScholarDigital LibraryDigital Library
  52. N. Lu, I.-S. Choi, S.-H. Ko, and S.-D. Kim. 2012. An effective hierarchical PRAM-SLC-MLC hybrid solid state disk. In IEEE/ACIS 11th International Conference on Computer and Information Science. 113--118. Google ScholarGoogle ScholarDigital LibraryDigital Library
  53. S. Mittal, J. S. Vetter, and Dong Li. 2015. A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches. IEEE Transactions on Parallel and Distributed Systems 26, 6, 1524--1537. DOI:http://dx.doi.org/10.1109/TPDS.2014.2324563 Google ScholarGoogle ScholarDigital LibraryDigital Library
  54. J. C. Mogul, E. Argollo, M. Shah, and P. Faraboschi. 2009. Operating system support for NVM+DRAM hybrid main memory. In Proceedings of the 12th Workshop on Hot Topics in Operating Systems (HatOS’09). 18--20. Google ScholarGoogle ScholarDigital LibraryDigital Library
  55. I. Moraru, D. G. Andersen, M. Kaminsky, N. Tolia, P. Ranganathan, and N. Binkert. 2013. Consistent, durable, and safe memory management for byte-addressable non volatile main memory. In Proceedings of the 1st ACM SIGOPS Conference on Timely Results in Operating Systems (TRIOS’13). ACM, New York, NY, Article 1, 17 pages. DOI:http://dx.doi.org/10.1145/2524211.2524216 Google ScholarGoogle ScholarDigital LibraryDigital Library
  56. D. Narayanan and O. Hodson. 2012. Whole-system persistence. In Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’12). Google ScholarGoogle ScholarDigital LibraryDigital Library
  57. S. Oikawa. 2013. Integrating memory management with a file system on a non-volatile main memory system. In Proceedings of the 28th Annual ACM Symposium on Applied Computing (SAC’13). ACM, New York, NY, 1589--1594. DOI:http://dx.doi.org/10.1145/2480362.2480660 Google ScholarGoogle ScholarDigital LibraryDigital Library
  58. Oracle. 2010. Oracle Berkeley DB downloads. Retrieved March 30, 2016 from http://www.oracle.com/technology/products/berkeley-db/index.html.Google ScholarGoogle Scholar
  59. Y. Park, S.-H. Lim, C. Lee, and K. H. Park. 2008. PFFS: A scalable flash memory file system for the hybrid architecture of phase-change RAM and NAND flash. In Proceedings of the 2008 ACM Symposium on Applied Computing (SAC’08). Google ScholarGoogle ScholarDigital LibraryDigital Library
  60. Y. Park, S. K. Park, and K. H. Park. 2010. Linux kernel support to exploit phase change memory. In Linux Symposium.Google ScholarGoogle Scholar
  61. S. Pelley, T. F. Wenisch, B. T. Gold, and B. Bridge. 2013. Storage management in the NVRAM era. Proceedings of the VLDB Endowment 7, 2. Google ScholarGoogle ScholarDigital LibraryDigital Library
  62. M. K. Qureshi. 2011. Pay-as-you-go: Low-overhead hard-error correction for phase change memories. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’11). Google ScholarGoogle ScholarDigital LibraryDigital Library
  63. M. K. Qureshi, J. Karidis, M. Fraceschini, V. Srinivasan, L. Lastras, and B. Abali. 2009. Enhancing lifetime and security of phase change memories via start-gap wear leveling. In Proceedings of the International Symposium on Microarchitecture. Google ScholarGoogle ScholarDigital LibraryDigital Library
  64. M. K. Qureshi, M. F. Michele, and A. L.-M. Luis. 2010. Improving read performance of phase change memories via write cancellation and write pausing. In HPCA’10.Google ScholarGoogle Scholar
  65. M. K. Qureshi, A. Seznec, L. A. Lastras, and M. M. Franceschini. 2011. Practical and secure PCM systems by online detection of malicious write streams. In IEEE 17th International Symposium on High Performance Computer Architecture (HPCA’11), Vol. 37. 478--489. Google ScholarGoogle ScholarDigital LibraryDigital Library
  66. M. K. Qureshi, V. Srinivasan, and J. A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09). New York, NY, 24--33. Google ScholarGoogle ScholarDigital LibraryDigital Library
  67. L. Ramos, E. Gorbatov, and R. Bianchini. 2011. Page placement in hybrid memory systems. In ICS’11. 85--95. Google ScholarGoogle ScholarDigital LibraryDigital Library
  68. P. Ranganathan. 2011. From microprocessors to nanostores: Re- thinking data-centric systems. IEEE Computer 44, 1, 39--48. Google ScholarGoogle ScholarDigital LibraryDigital Library
  69. S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y.-C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, and C. H. Lam. 2008. Phase-change random access memory: A scalable technology. IBM Journal of Research and Development 52, 4.5, 465--479. Google ScholarGoogle ScholarDigital LibraryDigital Library
  70. S. Raoux, F. Xiong, M. Wuttig, and E. Pop. 2014. Phase change materials and phase change memory. MRS Bulletin 39, 8, 703--710. DOI:http://dx.doi.org/10.1557/mrs.2014.139Google ScholarGoogle ScholarCross RefCross Ref
  71. D. A. Roberts. 2011. Efficient Data Center Architectures Using Non-Volatile Memory and Reliability Techniques). Ph.D. Dissertation. The University of Michigan, Ann Arbor, MI. Google ScholarGoogle ScholarDigital LibraryDigital Library
  72. S. Schechter, H. L. Gabriel, K. Strauss, and D. Burger. 2010. Use ECP, not ECC, for hard failures in resistive memories. In ISCA. Google ScholarGoogle ScholarDigital LibraryDigital Library
  73. R. Sears and E. Brewer. 2006. Stasis: Flexible transactional storage. In OSDI’06: Proceedings of the 7th Symposium on Operating Systems Design and Implementation. USENIX Association, Berkeley, CA, 29C--44. DOI:http://dx.doi.org/10.1109/IEDM.2009.5424263 Google ScholarGoogle ScholarDigital LibraryDigital Library
  74. D. Sengupta, Q. Wang, H. Volos, L. Cherkasova, J. Li, G. Magalhaes, and K. Schwan. 2015. A framework for emulating non-volatile memory systems with different performance characteristics. In Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering (ICPE’15). ACM, New York, NY, 317--320. DOI:http://dx.doi.org/10.1145/2668930.2695529 Google ScholarGoogle ScholarDigital LibraryDigital Library
  75. N. H. Seong, D. H. Woo, and H.-H. S. Lee. 2010a. Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In ISCA’10, Vol. 37. Google ScholarGoogle ScholarDigital LibraryDigital Library
  76. N. H. Seong, D. H. Woo, V. Srinivasan, J. A. Rivers, and H.-H. S. Lee. 2010b. SAFER: Stuck-at-fault error recovery for memories. In Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 115--124. Google ScholarGoogle ScholarDigital LibraryDigital Library
  77. N. H. Seong, S. Yeo, and H.-H. S. Lee. 2013. Tri-level-cell phase change memory: Toward an efficient and reliable memory system. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA’13). ACM, New York, NY, 440--451. http://dl.acm.org/citation.cfm?id=2485960. Google ScholarGoogle ScholarDigital LibraryDigital Library
  78. A. Seznec. 2010. A phase change memory as a secure main memory. IEEE Computer Architecture Letters 9, 1, 5--8. Google ScholarGoogle ScholarDigital LibraryDigital Library
  79. G. Sun, D. Niu, J. Ouyang, and Y. Xie. 2011. A frequent-value based PRAM memory architecture. In Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASPDAC’11). IEEE Press, Piscataway, NJ, 211--216. http://dl.acm.org/citation.cfm?id=1950815.1950867. Google ScholarGoogle ScholarDigital LibraryDigital Library
  80. S. Venkataraman, N. Tolia, P. Ranganathan, and R. H. Campbell. 2011. Consistent and durable data structures for non-volatile byte-addressable memory. In Proceedings of the 9th USENIX Conference on File and Stroage Technologies (FAST’11). USENIX Association, Berkeley, CA, 5--5. http://dl.acm.org/citation.cfm?id=1960475.1960480. Google ScholarGoogle ScholarDigital LibraryDigital Library
  81. H. Volos, A. J. Tack, and M. M. Swift. 2011. Mnemosyne: Lightweight persistent memory. In SIGARCH Computer Architecture News, Vol. 39. Google ScholarGoogle ScholarDigital LibraryDigital Library
  82. J. Wang, X. Dong, G. Sun, D. Niu, and Y. Xue. 2011. Energy-efficient multi-level cell phase-change memory system with data encoding. In IEEE 29th International Conference on Computer Design (ICCD’11). IEEE, 175--182. Google ScholarGoogle ScholarDigital LibraryDigital Library
  83. T. Wang, D. Liu, Y. Wang, and Z. Shao. 2015. Towards write-activity-aware page table management for non-volatile main memories. ACM Transactions on Embedded Computing Systems 14, 2, Article 34, 23 pages. DOI:http://dx.doi.org/10.1145/2697394 Google ScholarGoogle ScholarDigital LibraryDigital Library
  84. X. Wu, J. Li, L. Zhang, E. Speight, and Y. Xie. 2009a. Hybrid cache architecture with disparate memory technologies. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09). New York, NY, 34--45. Google ScholarGoogle ScholarDigital LibraryDigital Library
  85. X. Wu, J. Li, L. Zhang, E. Speight, and Y. Xie. 2009b. Power and performance of read-write aware hybrid caches with non-volatile memories. In Proceedings of Design Automation and Test in Europe (DATE’09). 737--742. Google ScholarGoogle ScholarDigital LibraryDigital Library
  86. X. Wu and A. L. N. Reddy. 2011. SCMFS: A file system for storage class memory. In Proceedings of International Conference for High Performance Computing, Networking, Storage and Analysis (SC’11). ACM, New York, NY, Article 39, 11 pages. DOI:http://dx.doi.org/10.1145/2063384.2063436 Google ScholarGoogle ScholarDigital LibraryDigital Library
  87. N. Yamada, E. Ohno, N. Akahira, K. Nishiuchi, K. Nagata, and M. Takao. 1987. High speed overwritable phase change optical disk material. Japanese Journal of Applied Physics Supplement 26, 8, 61C66.Google ScholarGoogle Scholar
  88. B. Yang, J. Lee, J. Kim, J. Cho, S. Lee, and B. Yu. 2007. A low power phase change random access memory using a data comparison write scheme. In ISCAS’07.Google ScholarGoogle Scholar
  89. J. Yang, Q. Wei, C. Chen, C. Wang, K. L. Yong, and B. He. 2015. NV-tree: Reducing consistency cost for NVM-based single level systems. In 13th USENIX Conference on File and Storage Technologies (FAST’15). USENIX Association, Santa Clara, CA, 167--181. https://www.usenix.org/conference/fast15/technical-sessions/presentation/yang. Google ScholarGoogle ScholarDigital LibraryDigital Library
  90. D. H. Yoon, N. Muralimanohar, J. Chang, P. Ranganathan, N. P. Jouppi, and M. Erez. 2011. FREE-p: Protecting non-volatile memory against both hard and soft errors. In HPCA’11. Google ScholarGoogle ScholarDigital LibraryDigital Library
  91. H. Yoon, J. Meza, R. Ausavarungnirun, R. A. Harding, and O. Mutlu. 2012. Row buffer locality aware caching policies for hybrid memories. In Proceedings of the 30th IEEE International Conference on Computer Design (ICCD’12). Montreal, Quebec, Canada, 1--8. Google ScholarGoogle ScholarDigital LibraryDigital Library
  92. H. Yoon, N. Muralimanohar, J. Meza, O. Mutlu, and N. P. Jouppi. 2013. Techniques for Data Mapping and Buffering to Exploit Asymmetry in Multi-Level Cell (Phase Change) Memory. SAFARI Technical Report 2013-002. Computer Architecture Lab (CALCM) at Carnegie Mellon University.Google ScholarGoogle Scholar
  93. J. Zhao, S. Li, D. H. Yoon, Y. Xie, and N. P. Jouppi. 2013. Kiln: Closing the performance gap between systems with and without persistence support. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’13). ACM, New York, NY, 421--432. DOI:http://dx.doi.org/10.1145/2540708.2540744 Google ScholarGoogle ScholarDigital LibraryDigital Library
  94. M. Zhao, L. Jiang, Y. Zhang, and C. J. Xue. 2014a. SLC-enabled wear leveling for MLC PCM considering process variation. In Proceedings of the 51st Annual Design Automation Conference (DAC’14). ACM, New York, NY, Article 36, 6 pages. DOI:http://dx.doi.org/10.1145/2593069.2593217 Google ScholarGoogle ScholarDigital LibraryDigital Library
  95. M. Zhao, L. Shi, C. Yang, and C. J. Xue. 2014b. Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory. In Proceedings of the 2014 32nd IEEE International Conference on Computer Design (ICCD’14). IEEE, 16--21.Google ScholarGoogle Scholar
  96. M. Zhao, Y. Xue, C. Yang, and C. J. Xue. 2015. Minimizing MLC PCM write energy for free through profiling-based state remapping. In Proceedings of the 20th Annual Asia and South Pacific Design Automation Conference (ASP-DAC’15). IEEE, 502--507.Google ScholarGoogle Scholar
  97. K. Zhong, D. Liu, L. Long, X. Zhu, W. Liu, Q. Zhuge, and E. H.-M. Sha. 2015. nCode: Limiting harmful writes to emerging mobile NVRAM through code swapping. In Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE’& Exhibition (DATE’’15). EDA Consortium, San Jose, CA, 1305--1310. http://dl.acm.org/citation.cfm?id=2755753.2757117. Google ScholarGoogle ScholarDigital LibraryDigital Library
  98. K. Zhong, T. Wang, X. Zhu, L. Long, D. Liu, W. Liu, Z. Shao, and E. H.-M. Sha. 2014. Building high-performance smartphones via non-volatile memory: The swap approach. In Proceedings of the 14th International Conference on Embedded Software (EMSOFT’14). ACM, New York, NY, Article 30, 10 pages. DOI:http://dx.doi.org/10.1145/2656045.2656049 Google ScholarGoogle ScholarDigital LibraryDigital Library
  99. P. Zhou, B. Zhao, J. Yang, and Y. Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. In 36th International Symposium on Computer Architecture (ISCA’09). 14--23. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Rethinking Computer Architectures and Software Systems for Phase-Change Memory

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    • Published in

      cover image ACM Journal on Emerging Technologies in Computing Systems
      ACM Journal on Emerging Technologies in Computing Systems  Volume 12, Issue 4
      Regular Papers
      July 2016
      394 pages
      ISSN:1550-4832
      EISSN:1550-4840
      DOI:10.1145/2856147
      • Editor:
      • Yuan Xie
      Issue’s Table of Contents

      Copyright © 2016 ACM

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      Publication History

      • Published: 12 May 2016
      • Accepted: 1 February 2016
      • Revised: 1 November 2015
      • Received: 1 July 2015
      Published in jetc Volume 12, Issue 4

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