ABSTRACT
Despite many attractive advantages, Null Convention Logic (NCL) remains to be a niche largely due to its high imple- mentation costs. Using emerging spintronic devices, this paper proposes a Domain-Wall-Motion-based NCL circuit design methodology that achieves approximately 30x and 8x improvements in energy efficiency and chip layout area, respectively, over its equivalent CMOS design, while main- taining similar delay performance for a 32-bit full adder. These advantages are made possible mostly by exploiting the domain wall motion physics to natively realize the hys- teresis critically needed in NCL. More Interestingly, this de- sign choice achieves ultra-high robustness by allowing spin- tronic device parameters to vary within a predetermined range while still achieving correct operations.
- P. A. Beerel, R. O. Ozdag, and M. Ferretti. A Designer's Guide to Asynchronous VLSI. Cambridge University Press, New York, NY, USA, 1st edition, 2010. Google ScholarDigital Library
- M.-C. Chang, M.-H. Hsieh, and P.-H. Yang. Low-power asynchronous ncl pipelines with fine-grain power gating and early sleep. Circuits and Systems II: Express Briefs, IEEE Transactions on, 61(12):957--961, Dec 2014.Google Scholar
- D. Fan, M. Sharad, A. Sengupta, and K. Roy. Hierarchical temporal memory based on spin-neurons and resistive memory for energy-efficient brain-inspired computing. arXiv preprint arXiv:1402.2902, 2014.Google Scholar
- . Fan, Y. Shim, A. Raghunathan, and K. Roy. STT-SNN: A spin-transfer-torque based soft-limiting non-linear neuron for low-power artificial neural networks. CoRR, abs/1412.8648, 2014..Google Scholar
- . Fong, S. Gupta, N. Mojumder, S. Choday, C. Augustine, and K. Roy. Knack: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque mram bit-cells. In Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pages 51--54, Sept 2011.Google Scholar
- S. Fukami, M. Yamanouchi, K.-J. Kim, T. Suzuki, N. Sakimura, D. Chiba, S. Ikeda, T. Sugibayashi, N. Kasai, T. Ono, and H. Ohno. 20-nm magnetic domain wall motion memory with ultralow-power operation. In Electron Devices Meeting (IEDM), 2013 IEEE International, pages 3.5.1--3.5.4, Dec 2013.Google ScholarCross Ref
- C. Jeong and S. Nowick. Optimal technology mapping and cell merger for asynchronous threshold networks. In Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on, pages 10 pp. 137, March 2006. Google ScholarDigital Library
- . Koyama, K. Ueda, K.-J. Kim, Y. Yoshimura, D. Chiba, K. Yamada, J.-P. Jamet, A. Mougin, A. Thiaville, S. Mizukami, et al. Current-induced magnetic domain wall motion below intrinsic threshold triggered by walker breakdown. Nature nanotechnology, 7(10):635--639, 2012.Google ScholarCross Ref
- M. Ligthart, K. Fant, R. Smith, A. Taubin, and A. Kondratyev. Asynchronous design using commercial hdl synthesis tools. In Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC '00, pages 114--, Washington, DC, USA, 2000. IEEE Computer Society. Google ScholarDigital Library
- F. Parsan, W. Al-Assadi, and S. Smith. Gate mapping automation for asynchronous null convention logic circuits. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 22(1):99--112, Jan 2014. Google ScholarDigital Library
- S. Smith, R. DeMara, J. Yuan, D. Ferguson, and D. Lamb. Optimization of NULL convention self-timed circuits. Integration, the VLSI Journal, 37(3):135--165, 2004. Google ScholarDigital Library
- Y. Zhang, W. S. Zhao, D. Ravelosona, J.-O. Klein, J. V. Kim, and C. Chappert. Perpendicular-magnetic-anisotropy cofeb racetrack memory. Journal of Applied Physics, 111(9):, 2012.Google Scholar
Index Terms
Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices
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