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A Task-Level Monitoring Framework for Multi-Processor Platforms

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Published:23 May 2016Publication History

ABSTRACT

In this paper, a monitoring framework for observing properties of tasks running on a multi-processor platform is proposed. We describe the implementation of the framework on a TLM-based virtual platform containing an ARM Cortex A9 multi-core instruction-set simulator and shared memory modules. An application model consisting of periodic tasks and communication channels is used to demonstrate the applicability of the monitoring framework. Based on the application model, we describe a method for deriving a monitor implementation at design time that is able to check the execution order and the platform mapping during run-time. The model is implemented on top of a POSIX-compatible real-time operating system and the monitor is instantiated as a TLM component in the virtual platform. The monitor implementation is then able to check the execution order and the platform mapping of the application against the specification at run-time. Finally, we discuss the monitoring capability and its contribution to a safety concept for fail-safe systems.

References

  1. O. Arnold and G. Fettweis. Adaptive runtime management of heterogenous MPSoCs: Analysis, acceleration and silicon prototype. In International Symposium on System-on-Chip (SoC'2014), pages 1--4. IEEE, Oct. 2014.Google ScholarGoogle ScholarCross RefCross Ref
  2. O. Arnold, B. Noethen, and G. Fettweis. Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit. In 2012 IEEE Computer Society Annual Symposium on VLSI, pages 249--254, Amherst, MA, USA, Aug. 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. J. Castrillon, D. Zhang, T. Kempf, B. Vanthournout, R. Leupers, and G. Ascheid. Task management in MPSoCs: an ASIP approach. In Proceedings of the 2009 International Conference on Computer-Aided Design (ICCAD'09), page 587. ACM Press, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. R. Dick, D. Rhodes, and W. Wolf. TGFF: task graphs for free. In Proceedings of the Sixth International Workshop on Hardware/Software Codesign (CODES/CASHE'98), pages 97--101, Mar. 1998. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. K. Grüttner, H. Kleen, F. Oppenheimer, A. Rettberg, and W. Nebel. Towards a Synthesis Semantics for SystemC Channels. In Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES/ISSS'10, pages 163--172, Scottsdale, Arizona, USA, 2010. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. R. Hankins, G. Chinya, J. Collins, P. Wang, R. Rakvic, Hong Wang, and J. Shen. Multiple Instruction Stream Processor. In Proceedings of the 33rd International Symposium on Computer Architecture (ISCA'06), pages 114--127. IEEE, 2006. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. P. Ittershagen, K. Grüttner, and W. Nebel. Mixed-Criticality System Modelling with Dynamic Execution Mode Switching. In Proceedings of the Forum on Specification and Design Languages (FDL'2015), Barcelona, Spain, 2015.Google ScholarGoogle ScholarCross RefCross Ref
  8. P. Kohout, B. Ganesh, and B. Jacob. Hardware support for real-time operating systems. In Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, page 45. ACM Press, 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. A. Kritikakou, C. Rochange, M. Faugère, C. Pagetti, M. Roy, S. Girbal, and D. G. Pérez. Distributed run-time WCET controller for concurrent critical tasks in mixed-critical systems. In Proceedings of the 22nd International Conference on Real-Time Networks and Systems (RTNS'14), pages 139--148. ACM Press, 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. S. Kumar, C. J. Hughes, and A. Nguyen. Carbon: architectural support for fine-grained parallelism on chip multiprocessors. In Proceedings of the 34th annual international symposium on Computer architecture, volume 34, pages 162--173, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. E. Lee and D. Messerschmitt. Synchronous data flow. Proceedings of the IEEE, 75(9):1235--1245, 1987.Google ScholarGoogle ScholarCross RefCross Ref
  12. D. Lo, M. Ismail, Tao Chen, and G. E. Suh. Slack-aware opportunistic monitoring for real-time systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS'2014), pages 203--214. IEEE, Apr. 2014.Google ScholarGoogle ScholarCross RefCross Ref
  13. C. Meenderinck and B. Juurlink. A Case for Hardware Task Management Support for the StarSS Programming Model. In 13th Euromicro Conference on Digital System Design (DSD'2010), pages 347--354. IEEE, Sept. 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. C. Meenderinck and B. Juurlink. Nexus: Hardware Support for Task-Based Programming. In 14th Euromicro Conference on Digital System Design (DSD'2011), pages 442--445. IEEE, Aug. 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. T. Nakano, A. Utama, M. Itabashi, A. Shiomi, and M. Imai. Hardware implementation of a real-time operating system. In Proceedings of TRON'95, pages 34--42. IEEE Comput. Soc. Press, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. M. Paolieri and R. Mariani. Towards functional-safe timing-dependable real-time architectures. In 2011 IEEE 17th International On-Line Testing Symposium, pages 31--36, Athens, Greece, July 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. SYSGO. PikeOS Hypervisor Product Datasheet, 2015.Google ScholarGoogle Scholar
  18. Windriver. VxWorks 6.2: Kernel Programmer's Guide, 2005.Google ScholarGoogle Scholar
  19. J. Wolf and T. Ungerer. An Optimized Timing and Control Flow Checker for Hard Real-Time Systems. In Proceedings of 2013 26th International Conference on Architecture of Computing Systems (ARCS'2013), Feb. 2013.Google ScholarGoogle Scholar
  1. A Task-Level Monitoring Framework for Multi-Processor Platforms

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      • Published in

        cover image ACM Other conferences
        SCOPES '16: Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems
        May 2016
        211 pages
        ISBN:9781450343206
        DOI:10.1145/2906363
        • Editor:
        • Sander Stuijk

        Copyright © 2016 ACM

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        New York, NY, United States

        Publication History

        • Published: 23 May 2016

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