ABSTRACT
Near threshold computing (NTC) has the potential to reduce the energy consumption by orders of magnitude. However, NTC designs suffer from a higher sensitivity to process variation and substantial performance degradation. In NTC, process variation affects the delays of different pipeline stages significantly, resulting in energy-inefficient designs. In this paper, we propose an energy-efficient variation-aware processor pipeline optimization, in which the pipeline stages are balanced by considering the impact of process variation during earlier design phases. This can lead to a well-balanced design and significant improvement in energy-efficiency. For this purpose, we employ an iterative variation-aware synthesis flow in which the synthesis tool is provided with variation information. Since the impact of process variation is considered during synthesis, our technique can improve the energy-efficiency by avoiding pessimistic guard band. Simulation results show that our technique can improve the energy-efficiency of OpenSPARC and FabScalar cores by 55% and 85%, respectively.
- Karpuzcu et.al. Energysmart: Toward energy-efficient manycores for near-threshold computing. In HPCA 2013. IEEE. Google ScholarDigital Library
- Pinckney et.al. Assessing the performance limits of parallelized near-threshold computing. In DAC. ACM, 2012. Google ScholarDigital Library
- Dreslinski et.al. Near-threshold computing: Reclaiming moore's law through energy efficient ic. IEEE Proc., 2010.Google Scholar
- Karpuzcu et.al. Coping with parametric variation at near-threshold voltages. Micro, IEEE, 2013. Google ScholarDigital Library
- Chun et.al. Shapeshifter: Dynamically changing pipeline width and speed to address process variations. In International Symposium on Microarchitecture. IEEE Computer Society, 2008. Google ScholarDigital Library
- Fojtik et.al. Bubble razor: Architecture-independent approach to timing-error detection and correction. In ISSCC, 2012.Google ScholarCross Ref
- Liu et.al. Process variation reduction for cmos logic operating at sub-threshold supply voltage. In Digital System Design, 2011. Google ScholarDigital Library
- Sato et.al. A simple flip-flop circuit for typical-case designs for dfm. In Quality Electronic Design, 2007. ISQED'07. IEEE. Google ScholarDigital Library
- Das et.al. Razorii: In situ error detection and correction for pvt and ser tolerance. Solid-State Circuits, 2009.Google Scholar
- Fabian Oboril and Mehdi B Tahoori. Aging-aware design of microprocessor instruction pipelines. TCAD, 2014.Google ScholarCross Ref
- Kaul et.al. Near-threshold voltage (ntv) design: opportunities and challenges. In DAC. ACM, 2012. Google ScholarDigital Library
- Chae et.al. A dynamic timing control technique utilizing time borrowing and clock stretching. In CICC, 2010. IEEE.Google ScholarCross Ref
- Choudhury et.al. Timber: Time borrowing and error relaying for online timing error resilience. In DATE, 2010. Google ScholarDigital Library
- Ernst et.al. Razor: circuit-level correction of timing errors for low-power operation. IEEE Micro, 2004. Google ScholarDigital Library
- Bowman et.al. Energy-efficient and metastability-immune timing-error detection and instruction-replay-based recovery circuits for dynamic-variation tolerance. In ISSCC. IEEE, 2008.Google ScholarCross Ref
- Tiwari et.al. Recycle:: pipeline adaptation to tolerate process variation. In Computer Architecture News. ACM, 2007. Google ScholarDigital Library
- Sartori et.al. Power balanced pipelines. In High Performance Computer Architecture (HPCA). IEEE, 2012. Google ScholarDigital Library
- Kuhn et.al. Process technology variation. Electron Devices, 2011.Google ScholarCross Ref
- Sunil Walia. Primetime® advanced ocv technology. Synopsys, Inc, 2009.Google Scholar
- Koppanalil et.al. A case for dynamic pipeline scaling. In international conference on Compilers, architecture, and synthesis for embedded systems. ACM, 2002. Google ScholarDigital Library
- Opensparc t1. http://www.oracle.com/technetwork/systems/opensparc/index.html. Accessed: 2016-01-30.Google Scholar
- Choudhary et.al. Fabscalar: Automating superscalar core design. IEEE Micro, 2012. Google ScholarDigital Library
Index Terms
- Maximizing Energy Efficiency in NTC by Variation-Aware Microprocessor Pipeline Optimization
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