Yin Li
ABSTRACT
With the nature of being memory hungry, in-memory key-value store is fundamentally subject to very high memory cost and energy consumption. Intuitively, the availability of a strong memory error correction at sufficiently small redundancy overhead could be leveraged to reduce memory cost and/or energy consumption. Nevertheless, current computing systems handle memory error correction solely in the hardware stack with very weak error correction strength. This paper for the first time studies the practical feasibility of implementing strong memory error correction code (ECC) in the software stack for in-memory key-value store without incurring significant speed performance penalty. This is fundamentally enabled by the low memory bandwidth utilization and relatively simple data structure of in-memory key-value store, which are actually shared with many other datacenter applications (e.g., Web search). This paper presents several design techniques to optimize software-based ECC implementation for in-memory key-value store, and elaborates on several important design issues. Using Memcached and RAMCloud as test vehicles, this work shows that the proposed design solution can improve the memory error correction strength by several orders of magnitude at similar (and even less) coding redundancy compared with current hardware-based design practice, and meanwhile incur less than 6% degradation of in-memory key-value store operational throughput.
- Zipf's law. https://en.wikipedia.org/wiki/ZipfGoogle Scholar
- Memcached:A distributed memory object caching system. http://memcached.org/, 2011.Google Scholar
- RAMCloud. http://ramcloud.stanford.edu, 2013.Google Scholar
- Redis. http://www.redis.io/, 2013.Google Scholar
- B. Atikoglu, Y. Xu, E. Frachtenberg, S. Jiang, and M. Paleczny. Workload analysis of a large-scale key-value store. In Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, pages 53--64, 2012. Google ScholarDigital Library
- M. Awasthi. Rethinking design metrics for datacenter DRAM. In Proc. of the International Symposium on Memory Systems (MEMSYS), pages 162--163, 2015. Google ScholarDigital Library
- N. Axelos, K. Pekmestzi, and D. Gizopoulos. Efficient memory repair using cache-based redundancy. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(12):2278--2288, 2012. Google ScholarDigital Library
- R. E. Blahut. Theory and Practice of Error Control Codes. Addison Wesley, 1984.Google Scholar
- K. Chakraborty and P. Mazumder. Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories. Prentice Hall, 2002.Google Scholar
- R. Clapp, M. Dimitrov, K. Kumar, V. Viswanathan, and T. Willhalm. Quantifying the performance impact of memory latency and bandwidth for big data workloads. In IEEE International Symposium on Workload Characterization, Oct. 2015. Google ScholarDigital Library
- B. F. Cooper, A. Silberstein, E. Tam, R. Ramakrishnan, and R. Sears. Benchmarking cloud serving systems with ycsb. In Proceedings of the 1st ACM symposium on Cloud computing, pages 143--154. ACM, 2010. Google ScholarDigital Library
- T. J. Dell. A white paper on the benefits of chipkill-correct ecc for pc server main memory. IBM Microelectronics Division, 1997.Google Scholar
- B. Fan, D. G. Andersen, and M. Kaminsky. MemC3: Compact and concurrent MemCache with dumber caching and smarter hashing. In USENIX Symposium on Networked Systems Design and Implementation (NSDI), April 2013. Google ScholarDigital Library
- M. Hsiao, D. Bossen, and R. Chien. Orthogonal latin square codes. IBM Journal of Research and Development, 14(4):390--394, July 1970. Google ScholarDigital Library
- V. Janapa Reddi, B. C. Lee, T. Chilimbi, and K. Vaid. Web search using mobile cores: Quantifying and mitigating the price of efficiency. In Proceedings of Annual International Symposium on Computer Architecture (ISCA), pages 314--325, 2010. Google ScholarDigital Library
- H. Lim, D. H. ad David G. Andersen, and M. Kaminsky. Mica: A holistic approach to fast in-memory key-value storage. In USENIX Symposium on Networked Systems Design and Implementation (NSDI), April 2014. Google ScholarDigital Library
- S. Lin and D. J. Costello. Error Control Coding: Fundamentals and Applications (2nd Ed.). Prentice Hall, 2004. Google ScholarDigital Library
- Y. Luo, S. Govindan, B. P. Sharma, M. Santaniello, J. Meza, A. Kansal, J. Liu, B. Khessib, K. Vaid, and O. Mutlu. Characterizing application memory error vulnerability to optimize datacenter cost via heterogeneous-reliability memory. In IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), pages 467--478, 2014. Google ScholarDigital Library
- K. T. Malladi, B. C. Lee, F. A. Nothaft, C. Kozyrakis, K. Periyathambi, and M. Horowitz. Towards energy-proportional datacenter memory with mobile DRAM. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 37--48, 2012. Google ScholarDigital Library
- P. J. Nair, D.-H. Kim, and M. K. Qureshi. Archshield: architectural framework for assisting DRAM scaling by tolerating high error rates. In International Symposium on Computer Architecture (ISCA), 2013. Google ScholarDigital Library
- D. M. Powers. Applications and explanations of zipf's law. In Proceedings of the joint conferences on new methods in language processing and computational natural language learning, pages 151--160. Association for Computational Linguistics, 1998. Google ScholarDigital Library
- S. Rumble, A. Kejriwal, and J. Ousterhout. Log-structured memory for DRAM-based storage. In Proc. of the USENIX Conference on File and Storage Technologies (FAST), pages 1--16, 2014. Google ScholarDigital Library
- S. M. Rumble. Memory and object management in RAMCloud. PhD thesis, Stanford University, March 2014.Google Scholar
- S. Schechter, G. H. Loh, K. Straus, and D. Burger. Use ECP, not ECC, for hard failures in resistive memories. In Proceedings of the International Symposium on Computer Architecture, pages 141--152, 2010. Google ScholarDigital Library
- H. Schirmeier, J. Neuhalfen, I. Korb, O. Spinczyk, and M. Engel. Rampage: Graceful degradation management for memory errors in commodity linux servers. In IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), pages 89--98, 2011. Google ScholarDigital Library
- D. Tang, P. Carruthers, Z. Totari, and M. Shapiro. Assessment of the effect of memory page retirement on system RAS against hardware faults. In International Conference on Dependable Systems and Networks, pages 365--370, 2006. Google ScholarDigital Library
- D. H. Yoon and M. Erez. Virtualized and flexible ECC for main memory. In ACM SIGARCH Computer Architecture News, volume 38, pages 397--408, 2010. Google ScholarDigital Library
- K. Zhang, K. Wang, Y. Yuan, L. Guo, R. Lee, and X. Zhang. MegaKV: A case for GPUs to maximize the throughput of in-memory key-value stores. Proceedings of the VLDB Endowment, 8(11):1226--1237, July 2015. Google ScholarDigital Library
Recommendations
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
VTS '09: Proceedings of the 2009 27th IEEE VLSI Test SymposiumECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space ...
Hotspot-Aware Hybrid Memory Management for In-Memory Key-Value Stores
Emerging Non-Volatile Memory (NVM) technologies promise much higher memory density and energy efficiency than DRAM, at the expense of higher read/write latency and limited write endurance. Hybrid memory systems composed of DRAM and NVM have the potential ...
Error patterns in MLC NAND flash memory: measurement, characterization, and analysis
DATE '12: Proceedings of the Conference on Design, Automation and Test in EuropeAs NAND flash memory manufacturers scale down to smaller process technology nodes and store more bits per cell, reliability and endurance of flash memory reduce. Wear-leveling and error correction coding can improve both reliability and endurance, but ...
Comments