Elsa Gonsiorowski
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Abstract
Gate-level circuit simulation is an important step in the design and validation of complex circuits. This step of the process relies on existing libraries for gate specifications. We start with a generic gate model for Rensselaer’s Optimistic Simulation System, a parallel discrete-event simulation framework. This generic model encompasses all functionality needed by optimistic simulation using reverse computation. We then describe a parser system that uses a standardized gate library to create a specific model for simulation. The generated model is composed of several functions, including those needed for an accurate model of timing behavior. To quantify the improvements that an automatically generated model can have over a hand written model, we compare two gate library models: an automatically generated lsi-10k library model and a previously investigated, handwritten, simplified gtech library model. We conclude that the automatically generated model is a more accurate model of actual hardware. In comparison to previous results, we find that the automatically generated model is able to achieve better optimistic simulation performance when measured against conservative simulation. To test the automatically generated model, we evaluate the performance of a simulation of a full-scale OpenSPARC T2 processor model. This model consists of nearly 6 million LPs. We achieve a peak performance of 1.63 million events per second during a conservative simulation. To understand the relatively weaker performance of optimistic simulation, we investigate hot spots of event activity and visually identify a workload imbalance.
- T. B. Ahmad and M. J. Ciesielski. 2014. Fast STA prediction-based gate-level timing simulation. In 2014 Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’14). 1--6. DOI:http://dx.doi.org/10.7873/DATE.2014.261 Google Scholar
Cross Ref
- Anjali Arya, V. V. Swaminathan, A Misra, and A. Kumar. 1985. Automatic generation of digital system schematic diagrams. In Proceedings of the 22nd ACM/IEEE Design Automation Conference (DAC’85). IEEE Computer Society, 388--395.Google Scholar
- Hervé Avril and Carl Tropper. 1995. Clustered time warp and logic simulation. In Proceedings of the 9th Workshop on Parallel and Distributed Simulation (PADS’95). IEEE Computer Society, 112--119. DOI:http://dx.doi.org/10.1145/214282.214317Google ScholarCross Ref
- Rajive Bagrodia, Yuan Chen, Vikas Jha, and Nicki Sonpar. 1995. Parallel gate-level circuit simulation on shared memory architectures. ACM SIGSIM Simul. Digest 25, 1 (1995), 170--174. Google ScholarDigital Library
- Rajive Bagrodia, Zheng Li, Vikas Jha, Yuan Chen, and Jason Cong. 1994. Parallel logic level simulation of VLSI circuits. In Proceedings of the 26th Conference on Winter Simulation (WSC’94). Society for Computer Simulation International, Orlando, FL, USA, 1354--1361. Google ScholarCross Ref
- Mary L. Bailey, Jack V. Briner, Jr., and Roger D. Chamberlain. 1994. Parallel logic simulation of VLSI systems. Comput. Surv. 26, 3 (Sept. 1994), 255--294. DOI:http://dx.doi.org/10.1145/185403.185424 Google ScholarDigital Library
- Peter D. Barnes, Jr., Christopher D. Carothers, David R. Jefferson, and Justin M. LaPre. 2013. Warp speed: Executing time warp on 1,966,080 cores. In Proceedings of the 2013 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation (PADS’13). ACM, 327--336. DOI:http://dx.doi.org/10.1145/2486092.2486134 Google ScholarDigital Library
- D. W. Bauer, C. D. Carothers, and A. Holder. 2009. Scalable time warp on blue gene supercomputers. In Proceedings of the 23rd ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation (PADS’09). IEEE Computer Society, 35--44. DOI:http://dx.doi.org/10.1109/PADS.2009.21 Google ScholarDigital Library
- David Beazley. 2000--2011. PLY: Python Lex-Yacc. Retrieved April 11, 2015 from http://www.dabeaz.com/ply/index.html. (2000--2011).Google Scholar
- Jack V. Briner, Jr., John L. Ellis, and Gershon Kedem. 1991. Breaking the barrier of parallel simulation of digital systems. In Proceedings of the 28th ACM/IEEE Design Automation Conference (DAC’91). ACM, 223--226. DOI:http://dx.doi.org/10.1145/127601.127669 Google ScholarDigital Library
- R. E. Bryant. 1977. Simulation of Packet Communication Architecture Computer Systems. Technical Report. Massachusetts Institute of Technology, Cambridge, MA.Google ScholarDigital Library
- C. D. Carothers, D. Bauer, and S. Pearce. 2000. ROSS: A high-performance, low memory, modular time warp system. In Proceedings of the 14th Workshop on Parallel and Distributed Simulation (PADS’00). IEEE Computer Society, 53--60. DOI:http://dx.doi.org/10.1109/PADS.2000.847144 Google ScholarCross Ref
- C. D. Carothers and K. S. Perumalla. 2010. On deciding between conservative and optimistic approaches on massively parallel platforms. In Proceedings of the 42nd Conference on Winter Simulation (WSC’10). 678--687. DOI:http://dx.doi.org/10.1109/WSC.2010.5679119 Google ScholarCross Ref
- C. D. Carothers, K. S. Perumalla, and R. M. Fujimoto. 1999a. Efficient optimistic parallel simulations using reverse computation. In Proceedings of the 13th Workshop on Parallel and Distributed Simulation (PADS’99). IEEE Computer Society, 126--135. DOI:http://dx.doi.org/10.1109/PADS.1999.766169 Google ScholarCross Ref
- Christopher D. Carothers, Kalyan S. Perumalla, and Richard M. Fujimoto. 1999b. Efficient optimistic parallel simulations using reverse computation. ACM Trans. Model. Comput. Simul. 9, 3 (July 1999), 224--253. DOI:http://dx.doi.org/10.1145/347823.347828 Google ScholarDigital Library
- Roger D. Chamberlain. 1995. Parallel logic simulation of VLSI systems. In Proceedings of the 32nd Annual ACM/IEEE Design Automation Conference (DAC’95). ACM, 139--143. DOI:http://dx.doi.org/10.1145/217474.217520 Google ScholarDigital Library
- K. M. Chandy and J. Misra. 1979. Distributed simulation: A case study in design and verification of distributed programs. IEEE Trans. Softw. Eng. SE-5, 5 (Sep. 1979), 440--452. DOI:http://dx.doi.org/10.1109/TSE.1979.230182 Google ScholarDigital Library
- K. M. Chandy and J. Misra. 1981. Asynchronous distributed simulation via a sequence of parallel computations. Commun. ACM 24, 4 (1981), 198--206. DOI:http://dx.doi.org/10.1145/358598.358613 Google ScholarDigital Library
- Yuan Chen, Vikas Jha, and Rajive Bagrodia. 1997. A multidimensional study on the feasibility of parallel switch-level circuit simulation. ACM SIGSIM Simul. Digest 27, 1 (June 1997), 46--54. DOI:http://dx.doi.org/10.1145/268823.268900 Google ScholarDigital Library
- Sorin C. Cismas, Kristan J Monsen, and Henry K. So. 2006. Automatic Code Generation for Integrated Circuit Design. (Feb. 2006). Patent No. 6,996,799. Filed Aug. 8, 2000, Issued Feb. 7, 2006.Google Scholar
- Alessandra Costa, Alessandro de Gloria, Paolo Faraboschi, and Mauro Olivieri. 1994. An evaluation system for distributed-time VHDL simulation. In Proceedings of the Eighth Workshop on Parallel and Distributed Simulation (PADS’94). ACM, 147--150. DOI:http://dx.doi.org/10.1145/182478.182582 Google ScholarDigital Library
- P. De, V. Mann, and U. Mittaly. 2009. Handling OS jitter on multicore multithreaded systems. In Proceedings of the IEEE International Symposium on Parallel Distributed Processing, 2009 (IPDPS’09). 1--12. DOI:http://dx.doi.org/10.1109/IPDPS.2009.5161046 Google ScholarDigital Library
- Richard M. Fujimoto. 1999. Parallel and Distributed Simulation Systems (1st ed.). John Wiley 8 Sons, Inc., New York, NY.Google Scholar
- Alan Gara, Matthias A. Blumrich, Dong Chen, GL-T Chiu, Paul Coteus, Mark E. Giampapa, Ruud A. Haring, Philip Heidelberger, Dirk Hoenicke, Gerard V. Kopcsay, and others. 2005. Overview of the blue gene/L system architecture. IBM J. Res. Dev. 49, 2.3 (2005), 195--212.Google ScholarDigital Library
- E. Gonsiorowski, C. Carothers, and C. Tropper. 2012. Modeling large scale circuits using massively parallel discrete-event simulation. In Proceedings of the 20th IEEE International Symposium on Modeling, Analysis Simulation of Computer and Telecommunication Systems (MASCOTS’12). 127--133. DOI:http://dx.doi.org/10.1109/MASCOTS.2012.24 Google ScholarDigital Library
- E. Gonsiorowski, J. LaPre, and C. Carothers. 2015. Improving accuracy and performance through automatic model generation for gate-level circuit PDES with reverse computation. In Proceedings of the 2015 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation (PADS’15). 87--96. DOI:http://dx.doi.org/10.1145/2769458.2769463 Google ScholarDigital Library
- Ruud A. Haring, Martin Ohmacht, Thomas W. Fox, Michael K. Gschwind, David L. Satterfield, Krishnan Sugavanam, Paul W. Coteus, Philip Heidelberger, Matthias A. Blumrich, Robert W. Wisniewski, et al. 2012. The IBM blue gene/Q compute chip. Micro. IEEE 32, 2 (2012), 48--60. Google ScholarDigital Library
- Jim Hogan. 2013. Hogan compares Palladium, Veloce, EVE ZeBu, Aldec, Bluespec, Dini. Retrieved November 19, 2015 from http://www.deepchip.com/items/0522-04.html.Google Scholar
- Akintayo O. Holder and Christopher D. Carothers. 2008. Analysis of time warp on a 32,768 processor IBM blue gene/L supercomputer. In Proceedings of the 20th European Modeling and Simulation Symposium (EMSS’08). CAL-TEK SRL, Amantea, Italy, 284--292.Google Scholar
- Kai hui Chang and C. Browy. 2012. Parallel logic simulation: Myth or reality? Computer 45, 4 (April 2012), 67--73. DOI:http://dx.doi.org/10.1109/MC.2011.385 Google ScholarDigital Library
- IEEE Standard for Verilog Hardware Description Language. 2006. IEEE Standard 1364-2005 (Revision of IEEE Standard 1364-2001). http://dx.doi.org/10.1109/IEEESTD.2006.99495. (2006). DOI:http://dx.doi.org/10.1109/IEEESTD.2006.99495. Google ScholarCross Ref
- IEEE Standard for Verilog Register Transfer Level Synthesis. 2002. IEEE Standard 1364.1-2002. http://dx.doi.org/10.1109/IEEESTD.2002.94220. (2002). DOI:http://dx.doi.org/10.1109/IEEESTD.2002.94220. Google ScholarCross Ref
- Ricki G. Ingalls. 1986. Automatic model generation. In Proceedings of the 18th Conference on Winter Simulation (WSC’86). ACM, Washington, DC, 677--685. Google ScholarDigital Library
- David R. Jefferson. 1985. Virtual time. ACM Trans. Program. Lang. Syst. 7, 3 (1985), 404--425. DOI:http://dx.doi.org/10.1145/3916.3988 Google ScholarDigital Library
- Sandip Kundu. 1998. Gatemaker: A transistor to gate level model extractor for simulation, automatic test pattern generation and verification. In Proceedings of the 1998 International Test Conference (ITC’98). IEEE Computer Society, Washington, DC, 372--381. Google ScholarCross Ref
- John Levine, Tony Mason, and Doug Brown. 1992. Lex 8 Yacc. O’Reilly 8 Associates, Sebastopol, CA, USA.Google Scholar
- L. Li, H. Huang, and C. Tropper. 2003. DVS: An object-oriented framework for distributed verilog simulation. In Proceedings of the 18th Workshop on Parallel and Distributed Simulation (PADS’03). IEEE Computer Society, 173--180. DOI:http://dx.doi.org/10.1109/PADS.2003.1207433 Google ScholarCross Ref
- Liberty, Version 2009.06. 2009. IEEE-ISTO. Retrieved May 12, 2015 from http://www.opensourceliberty.org.Google Scholar
- Yi-Bing Lin and Edward D. Lazowska. 1991. A study of time warp rollback mechanisms. ACM Trans. Model. Comput. Simul. 1, 1 (Jan. 1991), 51--72. DOI:http://dx.doi.org/10.1145/102810.102813 Google ScholarDigital Library
- Dragos Lungeanu and C.-J. Richard Shi. 1999. Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization. In Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design (ICCAD’99). IEEE Computer Society, 500--504.Google ScholarDigital Library
- S. Meraji, Wei Zhang, and C. Tropper. 2009. On the scalability of parallel verilog simulation. In Proceedings of the 38th International Conference on Parallel Processing (ICPP’09). IEEE Computer Society 365--370. DOI:http://dx.doi.org/10.1109/ICPP.2009.9 Google ScholarDigital Library
- R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham. 1993. VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 12, 3 (Mar 1993), 446--460. DOI:http://dx.doi.org/10.1109/43.215006 Google ScholarDigital Library
- David Nicol. 1993. The cost of conservative synchronization in parallel discrete event simulations. J. ACM 40, 2 (1993), 304--333. DOI:http://dx.doi.org/10.1145/151261.151266 Google ScholarDigital Library
- David Nicol and Philip Heidelberger. 1996. Parallel execution for serial simulators. ACM Trans. Model. Comput. Simul. 6, 3 (July 1996), 210--242. DOI:http://dx.doi.org/10.1145/235025.235031 Google ScholarDigital Library
- Samir Palnitkar. 2003. Verilog HDL: A Guide to Digital Design and Synthesis (2nd ed.). Prentice Hall Press, Upper Saddle River, NJ.Google Scholar
- Ishwar Parulkar, Alan Wood, Sun Microsystems, and Subhasish Mitra. 2008. OpenSPARC: An open platform for hardware reliability experimentation. In Proceedings of the Fourth Workshop on Silicon Errors in Logic System Effects (SELSE’08). IEEE Computer Society.Google Scholar
- Stewart Robinson. 2004. Simulation: The Practice of Model Development and Use. John Wiley 8 Sons, Hoboken, NY.Google ScholarDigital Library
- Larry Soulé and Anoop Gupta. 1991. An evaluation of the chandy-misra-bryant algorithm for digital logic simulation. ACM Trans. Model. Comput. Simul. 1, 4 (Oct. 1991), 308--347. DOI:http://dx.doi.org/10.1145/130611.130613 Google ScholarDigital Library
- Wen-king Su and Charles L. Seitz. 1988. Variants of the Chandy-Misra-Bryant Distributed Discrete-Event Simulation Algorithm. Technical Report. California Institute of Technology, Pasadena, CA, USA.Google Scholar
- Guilherme E. Vieira and Osmar César Júnior. 2005. A conceptual model for the creation of supply chain simulation models. In Proceedings of the 37th Conference on Winter Simulation (WSC’05). IEEE Computer Society. Google ScholarCross Ref
- Q. Xu and C. Tropper. 2005. XTW, A parallel and distributed logic simulator. In Proceedings of the 19th ACM/IEEE/SCS Workshop on Parallel and Distributed Simulation (PADS’05). ACM, 181--188. DOI:http://dx.doi.org/10.1109/PADS.2005.40 Google ScholarDigital Library
- Yuhao Zhu, Bo Wang, and Yangdong Deng. 2011. Massively parallel logic simulation with GPUs. ACM Trans. Des. Autom. Electron. Syst. 16, 3 (June 2011), Article 29 20 pages. DOI:http://dx.doi.org/10.1145/1970353.1970362 Google ScholarDigital Library
Index Terms
- Automatic Model Generation for Gate-Level Circuit PDES with Reverse Computation
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