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On the Accuracy of Stochastic Delay Bound for Network on Chip

Published:19 October 2017Publication History

ABSTRACT

Delay bound guarantee in network on chip (NoC) is important for hard real-time applications, and deterministic network calculus (DNC) is a effective tool for delay bound modeling. But for soft real-time applications, delay bound derivation using DNC is often over-pessimistic, resulting in too much chip area (e.g., router buffer) and power consumption; stochastic network calculus (SNC), on the contrary, improves the delay bound accuracy by providing stochastic service curves. Existing service models assume that contention takes place as long as there exist contention flows from different input channels requesting the same output channel. These models only consider flow paths in flows contention analyzing. We have observed that, beyond flow path contentions, the arrival rate also has deep influence on the flow contention in NoC, consequently affecting delay bound. In this paper, we further analyze the intrinsic factors affecting the flow contention, and propose a stochastic analytic model of per-flow delay bound to improve the calculation accuracy, according to both path and arrival rate. Within this model, the end-to-end delay bound is evaluated based on SNC. Experimental results show that our proposed model is both effective and accurate.

References

  1. L. Benini and G. De Micheli, "Networks on chips: a new soc paradigm," Computer, vol. 35, no. 1, pp. 70--78, 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. J.-Y. Le Boudec and P. Thiran, Network calculus: a theory of deterministic queuing systems for the internet, vol. 2050. Springer, 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Y. Qian, Z. Lu, and W. Dou, "Analysis of worst-case delay bounds for on-chip packet-switching networks," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, no. 5, pp. 802--815, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. G. Du, C. Zhang, Z. Lu, A. Saggio, and M. Gao, "Worst-case performance analysis of 2-d mesh nocs using multi-path minimal routing" in Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 123--132, ACM, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. A. Saggio, G. Du, X. Zhao, and Z. Lu, "Validating delay bounds in networks on chip: Tightness and pitfalls," in 2015 IEEE Computer Society Annual Symposium on VLSI, pp. 404--409, July 2015.Google ScholarGoogle Scholar
  6. X. Zhao and Z. Lu, "Empowering study of delay bound tightness with simulated annealing," in 2014 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1--6, March 2014. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Y. Jiang and Y. Liu, Stochastic network calculus, vol. 1. Springer, 2008.Google ScholarGoogle Scholar
  8. Z. Lu, Y. Yao, and Y. Jiang, "Towards stochastic delay bound analysis for nework-on-chip," in Eighth International Symposium on Networks-on-Chip, pp. 64--71, IEEE, 2014.Google ScholarGoogle Scholar
  9. Z. Qian, D. Juan, P. Bogdan, and C.-Y. Tsui, "A support vector regression (svr)-based latency model for network-on-chip (noc) architectures," IEEE transactions on computer-aided design of integrated circuits and systems, vol. 35, no. 3, pp. 471--484, 2016. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. M.Lai, L.Gao, N.Xiao, and Z. Wang, "An accurate and efficient performance analysis approach based on queuing model for network on chip," in ICCAD Dig. Tech. Papers, p. 563--570, ICCAD, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Y. Umit, B. Paul, and M. Radu, "An analytical approach for network-on-chip performance analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 2001--2013, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. K. Abbas Eslami, Z. Lu, and J. Axel, "An analytical latency model for networks-on-chip," in IEEE Educational Activities Department, pp. 113--123, November 2011.Google ScholarGoogle Scholar
  13. G. Min and M. Ould-Khaoua, "A performance model for wormhole-switched interconnection networks under self-similar traffic," Computers, IEEE Transactions on, vol. 53, no. 5, pp. 601--613, 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. B. Paul and M. Radu, "Workload characterization and its impact on multicore platform design," in Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on, pp. 231--240, Oct 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. B. Paul and M. Radu, "Statistical physics approaches for network-on-chip traffic characterization," in In Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, pp. 461--470, IEEE, 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. B. Paul, "Mathematical modeling and control of multifractal workloads for datacenter-on-a-chip optimization," in International Symposium on Networks-on-chip, pp. 1--8, ACM, 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. B. Paul and M. Radu, "Non-stationary traffic analysis and its implicationson multicore platform design," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 508--519, IEEE, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. R. L. Cruz, "A calculus for network delay. i. network elements in isolation," Information Theory, IEEE Transactions on, vol. 37, no. 1, pp. 114--131, 1991. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. J. Fahimeh, J. Axel, and L. Zhonghai, "Weighted round robin configuration for worst-case delay optimization in network-on-chip," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 3387--3400, May 2016. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. B. Paul, K. Miray, M. Radu, and O. Mutlu, "Quale: A quantum-leap inspired model for non-stationary analysis of noc traffic in chip multi-processors," in 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, pp. 241--248, May 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. J. Fahimeh, Z. Lu, and J. Axel, "Least upper delay bound for vbr flows in networks-on-chip with virtual channels," in Acm Transactions on Design Automation of Electronic Systems, pp. 1--34, June 2015. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. M. Bakhouya, S. Suboh, J. Gaber, T. El-Ghazawi, and S. Niar, "Performance evaluation and design tradeoffs of on-chip interconnect architectures," Simulation Modelling Practice and Theory, vol. 19, no. 6, pp. 1496--1505, 2011.Google ScholarGoogle ScholarCross RefCross Ref
  23. C. Jin-Wen, T. Liang, X. Hong-sheng, and Z. Jin, "A stochastic network calculus based approach for on-chip networks," in Control Conference (CCC), 2011 30th Chinese, pp. 4545--4549, IEEE, 2011.Google ScholarGoogle Scholar
  24. Y. Jiang, "Stochastic service curve and delay bound analysis: A single node case," in Teletraffic Congress (TIC), 2013 25th International, pp. 1--9, IEEE, 2013.Google ScholarGoogle Scholar
  25. S. Consortium et at, "The soclib project: An integrated system-on-chip modelling and simulation platform," tech. rep., Technical report, CNRS, 2003. http://www.soclib.fr.Google ScholarGoogle Scholar

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        • Published in

          cover image ACM Conferences
          NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip
          October 2017
          170 pages
          ISBN:9781450349840
          DOI:10.1145/3130218

          Copyright © 2017 ACM

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          Publication History

          • Published: 19 October 2017

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          NOCS '17 Paper Acceptance Rate14of44submissions,32%Overall Acceptance Rate14of44submissions,32%

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