Abstract
Many-core processors are expected to be hardware targets to support the execution of real-time applications. In a many-core processor, cores communicate through a Network-On-Chip (NoC), which offers high bandwidth and scalability, but also introduces contentions leading to additional variability to task execution times. Such contentions also strongly increase the pessimistic trend of worst case execution time estimation. Consequently, modeling and analysis of network contentions interferences on many-core processors is a challenge to support real-time applications. In this article, we formalize a dual task and flow model called DTFM. From the specification of a real-time application composed of a set of tasks and their communication dependencies, DTFM allows us to compute flow requirements and to assess predictability of the tasks. DTFM is extensible enough to be adapted to various NoCs and task models, allowing designers to compare candidate software and NoC architectures. Furthermore, we introduce an original validation approach based on the cross-use of a task level real-time scheduling analysis tool and a cycle-accurate SystemC NoC simulator.
- S. P. Azad, P. E. Behrad Niazmand, J. Raik, G. Jervan, and T. Hollstein. SoCDep2: a framework for dependable task deployment on many-core systems under mixed-criticality constraints. In Proceedings of 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pages 1--6, June 2016. Google ScholarCross Ref
- E. Bini and G. C. Buttazzo. Measuring the performance of schedulability tests. Real-Time Systems, 30(1-2):129--154, 2005. Google ScholarDigital Library
- B. d'Ausbourg, M. Boyer, E. Noulard, and C. Pagetti. Deterministic execution on many-core platforms: application to the scc. In Many-core Applications Researc Community Symposium (MARC), Dec 2011.Google Scholar
- P. H. Feiler and D. P. Gluch. Model-Based Engineering with AADL: An Introduction to the SAE Architecture Analysis & Design Language. Addison-Wesley, 2012.Google ScholarDigital Library
- C. Fotsing, F. Singhoff, A. Plantec, V. Gaudel, S. Rubini, S. Li, H. N. Tran, L. Lemarchand, P. Dissaux, and J. Legrand. Cheddar architecture description language. Lab-STICC Technical report, 2014.Google Scholar
- C. L. Liu and J. W. Layland. Scheduling algorithms for multiprogramming in a hard-real-time environment. Journal of the ACM (JACM), 20(1):46--61, 1973. Google ScholarDigital Library
- M. Sepúlveda, M. Strum, and W. Chau. Performance impact of QoSS (quality-of-security-service) inclusion for NoC-based systems. In 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pages 12--14, Oct 2009.Google Scholar
- Z. Shi. Real-Time Communication Services for Networks on Chip. PhD thesis, University of York, Nov 2009.Google Scholar
- Z. Shi and A. Burns. Real time communication analysis for on-chip networks with wormhole switching. In Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS), pages 161--170, Nov 2008. Google ScholarCross Ref
- Z. Shi and A. Burns. Real-time communication analysis with a priority share policy in on-chip networks. In Proceedings of the 21st Euromicro Conference on Real-Time Systems (ECRTS), pages 3--12, July 2009. Google ScholarDigital Library
- F. Singhoff, J. Legrand, L. Nana, and L. Marcé. Cheddar: a flexible real-time scheduling framework. ACM SIGAda Ada Letters, 24(4):1--8, Dec 2004. Google ScholarDigital Library
- A. T. Tran and B. Baas. NoCTweak: a highly parameterizable simulator for early exploration of performance and energy of networks on-chip. Technical Report ECE-VCL-2012-2, VLSI Computation Lab, ECE Department, University of California, Davis, July 2012. http://www.ece.ucdavis.edu/vcl/pubs/2012.07.techreport.noctweak/.Google Scholar
Index Terms
- DTFM: a flexible model for schedulability analysis of real-time applications on NoC-based architectures
Recommendations
PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness
The authors address the design and performance analysis of partial-multiple-bus interconnection networks. They are bus architectures that have evolved from the multiple-bus structure by dividing buses into groups and reducing bus connections. Their ...
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip
Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. ...
A High-Throughput Distributed Shared-Buffer NoC Router
Microarchitectural configurations of buffers in routers have a significant impact on the overall performance of an on-chip network (NoC). This buffering can be at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or ...
Comments