Ilgweon Kang
ABSTRACT
As pin accessibility encounters more challenges due to the less number of tracks, higher pin density, and more complex design rules, routability has become one bottleneck of sub-10nm designs. Thus, we need a new design methodology for fast turnaround in analyzing the feasibility of the layout architecture, e.g., design rules and patterns of pin assignment. In this paper, we propose a novel framework that efficiently identifies the design rule-correct routability by creating well-organized formulation. We start with a new SAT-friendly ILP formulation which satisfies conditional design rules. In the ILP-to-SAT conversion stage, we reduce the complexity of the SAT problem by utilizing a logic minimizer and further refining the SAT formula. We demonstrate that our framework performs the routability analysis within 0.24% of ILP runtime on average, while guaranteeing the precise assessment of the routability.
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