- 1. Agrawal, D.P. and Rao, T.R.N., "On Multiple Oper and Addition of Signed Binary Numbers," IEEE Trans. on Computers, Vol. C-27, No. 11, November 1978, pp. 1068-1070.Google Scholar
- 2. Agrawal, F.P. and Reddy, V.U., "Log-Sum Multiplier," National Computer Conference, 1976, pp. 783-787.Google Scholar
- 3. Booth, A.D., "A Signed Binary Multiplication Technique," Quart. J. Mech. Appl. Math, Vol. 4, Pt. 2, 1951.Google ScholarCross Ref
- 4. Brent, R.P. and Kung, H.T., "The Area Time Complexity of Binary Multiplication," Journal of the ACM, Vol. 28, No. 3, July 1981, pp. 521-534. Google ScholarDigital Library
- 5. Brubaker, T.A. and Becker, J.C., "Multiplication Using Logarithms Implemented with Read-Only Memory," IEEE Trans. on Computers, August 1975, pp. 701-705.Google Scholar
- 6. Cappello, P.R. and Steiglltz, K., "A VLSI Layout for a Pipelined Dadda Multiplier," ACM Trans. on Computer Systems, May 1983, pp. 157-174. Google ScholarDigital Library
- 7. Dadda, L., "Some Schemes for Parallel Multipliers," Alta Frequenza, Vol. 34, May 1965, pp. 349-356.Google Scholar
- 8. Deverell, J., "Pipeline Iterative Arithmetic Arrays," IEEE Trans. on Computers, March 1978, pp. 317-322.Google Scholar
- 9. Gajski, D.D., "Parallel Compressors," IEEE Trans. On Computers, May 1980, pp. 393-398.Google ScholarDigital Library
- 10. Guild, H.H., "Fully Iterative Fast Array for Binary Multiplication and Addition," Electronics Letters, June 1969, pp. 263.Google Scholar
- 11. Habibi, A. and Wintz, P.A., "Fast Multipliers," IEEE Trans. on Computers, February 1970, pp. 153-160.Google ScholarDigital Library
- 12. Hallin, T.G. and Flynn, M.J., "Pipelinlng of Arithmetic Functions," IEEE Trans. on Computers, August 1972, pp. 880-886.Google ScholarDigital Library
- 13. Hurson, A.R. and Dhall, S.K., "A Pipelined Multiplication Unit and Its Hardware Architecture," Technical Report, University of Oklahoma, Norman, Oklahoma, 1984.Google Scholar
- 14. Hwang, K., Computer Arithmetic, Principles, Architecture, and Design. John Wiley and Sons, 1979. Google ScholarDigital Library
- 15. Iwamura, Jun. et. al., "A 16 - Bit CMOS/SOS Multiplier-Accumulator," IEEE, 1982, pp. 151-154.Google Scholar
- 16. Luk, W.K., "A Regular Layout for Parallel Multiplier of O(log2n) Time," in VLSI Systems and Computations, Computer Science Press, 1981, pp. 317-326.Google Scholar
- 17. Majithia, J.C. and Kitai, R., "An Iterative Array for Multiplications of Signed Binary Numbers," IEEE Trans. on Computers, February 1971, pp. 214-216.Google ScholarDigital Library
- 18. Mead, C. and Conway, L., Introduction to VLSI Systems, Addison Wesley, 1980. Google ScholarDigital Library
- 19. Mitchell, Jr., J.N. "Computer Multiplication and Division Using Binary Logarithms," IEEE Trans. on Electronic Computers, August 1962, pp. 512-517.Google ScholarCross Ref
- 20. Obermann, R.M.M., Digital Circuits for Binary Arithmetic, A Halsted Press Book, 1979.Google Scholar
- 21 . Reusens, P., Ku, W.H. and Mao, Y.H., "Fixed Point High Parallel Multipliers in VLSI," in VLSI Systems and Computations, Computer Science Press, 1981, pp. 301- 310.Google Scholar
- 22. Rubinfield, L.R., "A Proof of the Modified Booth's Algorithms for Multiplication," IEEE Trans. on Computers, October 1975, pp. 1014-1015.Google ScholarDigital Library
- 23. Stenzel, W.J., Kubitz, W.J. and Garcia, G.H., "A Compact High Speed Multiplication Scheme," IEEE Trans. on Computers, Oct. 1977, pp. 948-957.Google ScholarDigital Library
- 24. Swartzlander, Jr., E.E., "The Quasi-Serial Multiplier," IEEE Trans. on Computers, Vol. C-22, No. 4, April 1973, pp. 317-321.Google Scholar
- 25. Swartzlander, Jr., E.E., "Merged Arithmetic for Signal Processing," Proceedings of IEEE Fourth Symposium on Computer Arithmetic, Santa Monica, CA, 1978.Google Scholar
- 26. Trivedi, K.S. and Ercegovac, M.D., "On-Line Algorithms for Division and Multiplication," IEEE Trans. on Computers, July 1977, pp. 681-687.Google ScholarDigital Library
- 27. Wallace, C.S., "A Suggestion for a Fast Multiplier," IEEE Trans. on Electronic Computers, February 1964, pp. 14-17.Google ScholarCross Ref
- 28. Waser, S. and Flynn, M.J., Introduction to Arithmetic for Digital Systems Designers, Holt, Reinhart and Winston, New York, 1982. Google ScholarDigital Library
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